
MOTOROLA
10-8
MC68HC05B6
Rev. 4
CPU CORE AND INSTRUCTION SET
10
Table 10-7 Instruction set (1 of 2)
Mnemonic
Addressing modes
Condition codes
INH
IMM
DIR
EXT
REL
IX
IX1
IX2
BSC BTB
H
I
N
Z
C
ADC
ADD
AND
ASL
ASR
BCC
BCLR
BCS
BEQ
BHCC
BHCS
BHI
BHS
BIH
BIL
BIT
BLO
BLS
BMC
BMI
BMS
BNE
BPL
BRA
BRN
BRCLR
BRSET
BSET
BSR
CLC
0
CLI
0
CLR
0
1
CMP
Condition code symbols
H
Half carry (from bit 3)
Tested and set if true,
cleared otherwise
I
Interrupt mask
Not affected
N
Negate (sign bit)
?
Load CCR from stack
Z
Zero
0
Cleared
C
Carry/borrow
1
Set
Not implemented
Address mode abbreviations
BSC Bit set/clear
IMM
Immediate
BTB Bit test & branch
IX
Indexed (no offset)
DIR
Direct
IX1
Indexed, 1 byte offset
EXT Extended
IX2
Indexed, 2 byte offset
INH
Inherent
REL
Relative
TPG
122
05B6Book Page 8 Tuesday, April 6, 1999 8:24 am