- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄4003 > MC68HC001EI16 (Freescale Semiconductor)IC MPU 16BIT 16MHZ 68-PLCC PDF資料下載
參數(shù)資料
| 型號(hào)： | MC68HC001EI16 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 183/189頁 |
| 文件大小： | 0K |
| 描述： | IC MPU 16BIT 16MHZ 68-PLCC |
| 標(biāo)準(zhǔn)包裝： | 18 |
| 系列： | M680x0 |
| 處理器類型： | M680x0 32-位 |
| 速度： | 16MHz |
| 電壓： | 3.3V，5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 68-PLCC（25x25） |
| 包裝： | 管件 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁當(dāng)前第183頁第184頁第185頁第186頁第187頁第188頁第189頁
6- 8
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
MOTOROLA
6.2.3 Multiple Exceptions
These paragraphs describe the processing that occurs when multiple exceptions arise
simultaneously. Exceptions can be grouped by their occurrence and priority. The group 0
exceptions are reset, bus error, and address error. These exceptions cause the instruction
currently being executed to abort and the exception processing to commence within two
clock cycles. The group 1 exceptions are trace and interrupt, privilege violations, and
illegal instructions. Trace and interrupt exceptions allow the current instruction to execute
to completion, but pre-empt the execution of the next instruction by forcing exception
processing to occur. A privilege-violating instruction or an illegal instruction is detected
when it is the next instruction to be executed. The group 2 exceptions occur as part of the
normal processing of instructions. The TRAP, TRAPV, CHK, and zero divide exceptions
are in this group. For these exceptions, the normal execution of an instruction may lead to
exception processing.
Group 0 exceptions have highest priority, whereas group 2 exceptions have lowest
priority. Within group 0, reset has highest priority, followed by address error and then bus
error. Within group 1, trace has priority over external interrupts, which in turn takes priority
over illegal instruction and privilege violation. Since only one instruction can be executed
at a time, no priority relationship applies within group 2.
The priority relationship between two exceptions determines which is taken, or taken first,
if the conditions for both arise simultaneously. Therefore, if a bus error occurs during a
TRAP instruction, the bus error takes precedence, and the TRAP instruction processing is
aborted. In another example, if an interrupt request occurs during the execution of an
instruction while the T bit is asserted, the trace exception has priority and is processed
first. Before instruction execution resumes, however, the interrupt exception is also
processed, and instruction processing finally commences in the interrupt handler routine.
A summary of exception grouping and priority is given in Table 6-3.
As a general rule, the lower the priority of an exception, the sooner the handler routine for
that exception executes. For example, if simultaneous trap, trace, and interrupt exceptions
are pending, the exception processing for the trap occurs first, followed immediately by
exception processing for the trace and then for the interrupt. When the processor resumes
normal instruction execution, it is in the interrupt handler, which returns to the trace
handler, which returns to the trap execution handler. This rule does not apply to the reset
exception; its handler is executed first even though it has the highest priority, because the
reset operation clears all other exceptions.
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| FMC40DREI | CONN EDGECARD 80POS .100 EYELET |
| MC68HC001EI12 | IC MPU 16BIT 12MHZ 68-PLCC |
| MC68HC001EI10 | IC MPU 16BIT 10MHZ 68-PLCC |
| GMC50DTEH | CONN EDGECARD 100POS .100 EYELET |
| AMM22DREF | CONN EDGECARD 44POS .156 EYELET |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68HC001EI8 | 功能描述:微處理器 - MPU 16-BIT MPU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68HC001FN10 | 制造商:Rochester Electronics LLC 功能描述:16-BIT MPU - Bulk |
| MC68HC001FN12 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MC68HC001FN16 | 制造商:Rochester Electronics LLC 功能描述:16-BIT MPU - Bulk |
| MC68HC001FN16R2 | 制造商:Rochester Electronics LLC 功能描述:16-BIT MPU - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。