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| 型號： | MC68HC001CEI10 |
| 廠商： | Freescale Semiconductor |
| 文件頁數： | 4/189頁 |
| 文件大小： | 0K |
| 描述： | IC MPU 16BIT 10MHZ 68-PLCC |
| 標準包裝： | 18 |
| 系列： | M680x0 |
| 處理器類型： | M680x0 32-位 |
| 速度： | 10MHz |
| 電壓： | 3.3V，5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 68-LCC（J 形引線） |
| 供應商設備封裝： | 68-PLCC（25x25） |
| 包裝： | 管件 |
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6- 16
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
MOTOROLA
After the execution of the instruction is complete and before the start of the next
instruction, exception processing for a trace begins. A copy is made of the status register.
The transition to supervisor mode is made, and the T bit of the status register is turned off,
disabling further tracing. The vector number is generated to reference the trace exception
vector, and the current program counter and the copy of the status register are saved on
the supervisor stack. On the MC68010, the format/offset word is also saved on the
supervisor stack. The saved value of the program counter is the address of the next
instruction. Instruction execution commences at the address contained in the trace
exception vector.
6.3.9 Bus Error
A bus error exception occurs when the external logic requests that a bus error be
processed by an exception. The current bus cycle is aborted. The current processor
activity, whether instruction or exception processing, is terminated, and the processor
immediately begins exception processing. The bus error facility is identical on the all
processors; however, the stack frame produced on the MC68010 contains more
information. The larger stack frame supports instruction continuation, which supports
virtual memory on the MC68010 processor.
6.3.9.1 BUS ERROR. Exception processing for a bus error follows the usual sequence of
steps. The status register is copied, the supervisor mode is entered, and tracing is turned
off. The vector number is generated to refer to the bus error vector. Since the processor is
fetching the instruction or an operand when the error occurs, the context of the processor
is more detailed. To save more of this context, additional information is saved on the
supervisor stack. The program counter and the copy of the status register are saved. The
value saved for the program counter is advanced 2–10 bytes beyond the address of the
first word of the instruction that made the reference causing the bus error. If the bus error
occurred during the fetch of the next instruction, the saved program counter has a value in
the vicinity of the current instruction, even if the current instruction is a branch, a jump, or
a return instruction. In addition to the usual information, the processor saves its internal
copy of the first word of the instruction being processed and the address being accessed
by the aborted bus cycle. Specific information about the access is also saved: type of
access (read or write), processor activity (processing an instruction), and function code
outputs when the bus error occurred. The processor is processing an instruction if it is in
the normal state or processing a group 2 exception; the processor is not processing an
instruction if it is processing a group 0 or a group 1 exception. Figure 6-7 illustrates how
this information is organized on the supervisor stack. If a bus error occurs during the last
step of exception processing, while either reading the exception vector or fetching the
instruction, the value of the program counter is the address of the exception vector.
Although this information is not generally sufficient to effect full recovery from the bus
error, it does allow software diagnosis. Finally, the processor commences instruction
processing at the address in the vector. It is the responsibility of the error handler routine
to clean up the stack and determine where to continue execution.
If a bus error occurs during the exception processing for a bus error, an address error, or
a reset, the processor halts and all processing ceases. This halt simplifies the detection of
a catastrophic system failure, since the processor removes itself from the system to
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關代理商/技術參數 |
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| MC68HC001CEI8 | 功能描述:IC MPU 32BIT 8MHZ 68-PLCC RoHS:是 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:M680x0 標準包裝:1 系列:MPC85xx 處理器類型:32-位 MPC85xx PowerQUICC III 特點:- 速度:1.2GHz 電壓:1.1V 安裝類型:表面貼裝 封裝/外殼:783-BBGA，FCBGA 供應商設備封裝:783-FCPBGA（29x29） 包裝:托盤 |
| MC68HC001CFN8R2 | 制造商:Rochester Electronics LLC 功能描述: |
| MC68HC001EI10 | 功能描述:微處理器 - MPU 16-BIT MPU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68HC001EI12 | 功能描述:微處理器 - MPU 16-BIT MPU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68HC001EI16 | 功能描述:微處理器 - MPU 16-BIT MPU RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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