參數(shù)資料
型號: MC68HC000EI8R2
廠商: Freescale Semiconductor
文件頁數(shù): 187/189頁
文件大?。?/td> 0K
描述: IC MPU 16BIT 8MHZ 68-PLCC
標(biāo)準(zhǔn)包裝: 250
系列: M680x0
處理器類型: M680x0 32-位
速度: 8MHz
電壓: 3.3V,5V
安裝類型: 表面貼裝
封裝/外殼: 68-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 68-PLCC(25x25)
包裝: 帶卷 (TR)
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁第119頁第120頁第121頁第122頁第123頁第124頁第125頁第126頁第127頁第128頁第129頁第130頁第131頁第132頁第133頁第134頁第135頁第136頁第137頁第138頁第139頁第140頁第141頁第142頁第143頁第144頁第145頁第146頁第147頁第148頁第149頁第150頁第151頁第152頁第153頁第154頁第155頁第156頁第157頁第158頁第159頁第160頁第161頁第162頁第163頁第164頁第165頁第166頁第167頁第168頁第169頁第170頁第171頁第172頁第173頁第174頁第175頁第176頁第177頁第178頁第179頁第180頁第181頁第182頁第183頁第184頁第185頁第186頁當(dāng)前第187頁第188頁第189頁
6- 12
M68000 8-/16-/32-BIT MICROPROCESSORS USER'S MANUAL
MOTOROLA
interrupt priority mask is set at level 7. In the MC68010, the VBR is forced to zero. The
vector number is internally generated to reference the reset exception vector at location 0
in the supervisor program space. Because no assumptions can be made about the validity
of register contents, in particular the SSP, neither the program counter nor the status
register is saved. The address in the first two words of the reset exception vector is
fetched as the initial SSP, and the address in the last two words of the reset exception
vector is fetched as the initial program counter. Finally, instruction execution is started at
the address in the program counter. The initial program counter should point to the power-
up/restart code.
The RESET instruction does not cause a reset exception; it asserts the RESET signal to
reset external devices, which allows the software to reset the system to a known state and
continue processing with the next instruction.
6.3.2 Interrupts
Seven levels of interrupt priorities are provided, numbered from 1–7. All seven levels are
available except for the 48-pin version for the MC68008.
NOTE
The MC68008 48-pin version supports only three interrupt
levels: 2, 5, and 7. Level 7 has the highest priority.
Devices can be chained externally within interrupt priority levels, allowing an unlimited
number of peripheral devices to interrupt the processor. The status register contains a 3-
bit mask indicating the current interrupt priority, and interrupts are inhibited for all priority
levels less than or equal to the current priority.
An interrupt request is made to the processor by encoding the interrupt request levels 1–7
on the three interrupt request lines; all lines negated indicates no interrupt request.
Interrupt requests arriving at the processor do not force immediate exception processing,
but the requests are made pending. Pending interrupts are detected between instruction
executions. If the priority of the pending interrupt is lower than or equal to the current
processor priority, execution continues with the next instruction, and the interrupt
exception processing is postponed until the priority of the pending interrupt becomes
greater than the current processor priority.
If the priority of the pending interrupt is greater than the current processor priority, the
exception processing sequence is started. A copy of the status register is saved; the
privilege mode is set to supervisor mode; tracing is suppressed; and the processor priority
level is set to the level of the interrupt being acknowledged. The processor fetches the
vector number from the interrupting device by executing an interrupt acknowledge cycle,
which displays the level number of the interrupt being acknowledged on the address bus.
If external logic requests an automatic vector, the processor internally generates a vector
number corresponding to the interrupt level number. If external logic indicates a bus error,
the interrupt is considered spurious, and the generated vector number references the
spurious interrupt vector. The processor then proceeds with the usual exception
processing, saving the format/offset word (MC68010 only), program counter, and status
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.
相關(guān)PDF資料
PDF描述
MC68HC000EI8 IC MPU 16BIT 8MHZ 68-PLCC
IDT7140LA100C IC SRAM 8KBIT 100NS 48DIP
FMC50DRAN-S734 CONN EDGECARD 100PS .100 R/A SLD
MC68HC000EI20 IC MPU 16BIT 20MHZ 68-PLCC
MC68HC000EI12 IC MPU 16BIT 10MHZ 68-PLCC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC68HC000FN10 制造商:Freescale Semiconductor 功能描述:Microprocessor IC Processor Type:68xxx 3
MC68HC000FN12 制造商:Motorola Inc 功能描述: 制造商:MOTOROLA 功能描述:
MC68HC000FN16 功能描述:IC MPU 32BIT 16MHZ 68-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:M680x0 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點(diǎn):- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA(25x25) 包裝:托盤
MC68HC000FN16R2 功能描述:IC MPU 32BIT 16MHZ 68-PLCC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微處理器 系列:M680x0 標(biāo)準(zhǔn)包裝:2 系列:MPC8xx 處理器類型:32-位 MPC8xx PowerQUICC 特點(diǎn):- 速度:133MHz 電壓:3.3V 安裝類型:表面貼裝 封裝/外殼:357-BBGA 供應(yīng)商設(shè)備封裝:357-PBGA(25x25) 包裝:托盤
MC68HC000FN20 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Addendum to M68000 User Manual