Table of Contents
Paragraph
Number
Title
Page
Number
MOTOROLA
MC68360 USER’S MANUAL
xxi
Section 8
Scan Chain Test Access Port
8.1
8.2
8.3
8.4
8.4.1
8.4.2
8.4.3
8.4.4
8.4.5
8.5
8.6
Overview ................................................................................................. 8-1
TAP Controller......................................................................................... 8-2
Boundary Scan Register ......................................................................... 8-3
Instruction Register ............................................................................... 8-10
EXTEST ................................................................................................ 8-10
SAMPLE/PRELOAD.............................................................................. 8-10
BYPASS................................................................................................ 8-11
CLAMP.................................................................................................. 8-11
HI-Z ....................................................................................................... 8-11
QUICC Restrictions............................................................................... 8-11
Non-Scan Chain Operation................................................................... 8-12
Section 9
Applications
9.1
9.1.1
9.1.1.1
9.1.1.2
9.1.1.3
9.1.1.4
9.1.1.5
9.1.1.6
9.1.1.7
9.1.1.8
9.1.1.9
9.1.1.10
9.1.1.11
9.1.1.12
9.1.2
9.1.2.1
9.1.2.2
9.1.2.3
9.1.2.4
9.1.2.5
9.1.2.6
9.1.2.7
9.1.3
9.1.3.1
9.1.3.2
9.1.3.3
9.2
Minimum System Configuration .............................................................. 9-1
QUICC Hardware Configuration.............................................................. 9-1
QUICC Basic Accesses........................................................................... 9-1
Clocking Strategy.................................................................................... 9-3
Resetting the QUICC............................................................................... 9-3
Interrupts................................................................................................. 9-3
Bus Arbitration......................................................................................... 9-3
Breakpoint Generation. ........................................................................... 9-3
Bus Monitor Function. ............................................................................. 9-3
Spurious Interrupt Monitor....................................................................... 9-3
Software Watchdog................................................................................. 9-3
Double Bus Fault..................................................................................... 9-4
JTAG and Three-State............................................................................ 9-4
QUICC Serial Ports................................................................................. 9-4
Memory Interfaces................................................................................... 9-4
QUICC Memory Interface Pins................................................................ 9-4
Regular EPROM...................................................................................... 9-5
Flash EPROM. ........................................................................................ 9-5
SRAM...................................................................................................... 9-6
EEPROM................................................................................................. 9-7
DRAM SIMM. .......................................................................................... 9-8
DRAM Devices........................................................................................ 9-9
Software Configuration.......................................................................... 9-10
Basic Initialization.................................................................................. 9-10
Configuring the Memory Controller. ...................................................... 9-11
Using the QUICC in 16-Bit Data Bus Mode........................................... 9-12
How to take A QUICC Software Test-Drive........................................... 9-13
Step 1: Decide on Reset Stack Pointer and Initial Program Counter.... 9-13
Step 2: Stay in Supervisor Mode........................................................... 9-13
Step 3: Write the VBR........................................................................... 9-14