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參數(shù)資料
| 型號： | MC68EN360EM33L |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 10/14頁 |
| 文件大小： | 0K |
| 描述： | IC MPU W/ETHERNET 240-FQFP |
| 標(biāo)準(zhǔn)包裝： | 24 |
| 系列： | M683xx |
| 處理器類型： | M683xx 32-位 |
| 速度： | 33MHz |
| 電壓： | 5V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 240-BFQFP |
| 供應(yīng)商設(shè)備封裝： | 240-FQFP（32x32） |
| 包裝： | 托盤 |
fetch two word-length instructions in one bus cycle, filling the internal instruction queue more quickly. The
CPU32+ core can also read and write 32-bits of data in one bus cycle.
Although the CPU32+ instruction timings are improved, its instruction set is identical to that of the CPU32. It
will also execute the entire M68000 instruction set. It contains the same background debug mode (BDM)
features as the CPU32. No new compilers, assemblers, or other software support tools need be
implemented for the CPU32+; standard CPU32 tools can be used.
The CPU32+ delivers approximately 4.5 MIPS at 25 MHz, based on the standard (accepted) assumption that
a 10-MHz M68000 delivers 1 VAX MIPS. If an application requires more performance, the CPU32+ can be
disabled, allowing the rest of the QUICC to operate as an intelligent peripheral to a faster processor. The
QUICC provides a special mode called MC68040 companion mode to allow it to conveniently interface to
members of the M68040 family. This two-chip solution provides a 22-MIPS performance at 25 MHz.
The CPU32+ also offers automatic byte alignment features that are not offered on the CPU32. These
features allow 16 or 32-bit data to be read or written at an odd address. The CPU32+ automatically performs
the number of bus cycles required.
System Integration Module (SIM60)
The SIM60 integrates general-purpose features that would be useful in almost any 32-bit processor system.
The term “SIM60” is derived from the QUICC part number, MC68360. The SIM60 is an enhanced version of
the SIM40 that exists on the MC68340 and MC68330 devices.
First, new features, such as a DRAM controller and breakpoint logic, have been added. Second, the SIM40
was modified to support a 32-bit IMB as well as a 32-bit external system bus. Third, new configurations, such
as slave mode and internal accesses by an external master, are supported.
Although the QUICC is always a 32-bit device internally, it may be configured to operate with a 16-bit data
bus. Regardless of the choice of the system bus size, dynamic bus sizing is supported. Bus sizing allows 8-,
16-, and 32-bit peripherals and memory to exist in the 32-bit system bus mode and 8- and 16-bit peripherals
and memory to exist in the 16-bit system bus mode.
Communications Processor Module (CPM)
The CPM contains features that allow the QUICC to excel in communications and control applications. These
features may be divided into three sub-groups:
Communications Processor (CP)
Two IDMA Controllers
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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