參數(shù)資料
型號(hào): MC68CK338CPV14B1
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 14.4 MHz, MICROCONTROLLER, PQFP144
封裝: TQFP-144
文件頁數(shù): 121/133頁
文件大?。?/td> 817K
代理商: MC68CK338CPV14B1
MOTOROLA
MC68CK338
88
MC68CK338TS/D
NOTE
In order to count, the FCSM requires the CPSM clock signals to be present. On
coming out of reset, the FCSM does not count internal or external events until the
prescaler in the CPSM starts running (when the software sets the PRUN bit). This
allows all counters in the CTM6 submodules to be synchronized.
Figure 20 FCSM Block Diagram
6.7.1 FCSM Registers
The FCSM contains a status/interrupt/control register and a counter register. All unused bits and re-
served address locations return zero when read. Writing to unused bits and reserved address locations
has no effect.
COF — Counter Overflow Flag
This status flag indicates whether or not a counter overflow has occurred. An overflow is defined to be
the transition of the counter from $FFFF to $0000. If the IL field is non-zero, an interrupt request is gen-
erated when the COF bit is set.
0 = Counter overflow has not occurred
1 = Counter overflow has occurred
This flag is set only by hardware and cleared only by software or a system reset. To clear the flag, first
read the register with COF set to one, then write a zero to the bit. COF is cleared only if no overflow
occurs between the read and write operations.
FCSM3SIC — FCSM Status/Interrupt/Control Register
$YFF418
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
COF
IL[2:0]
IARB3
0
DRVA
DRVB
IN
0
CLK[2:0]
RESET:
0
U
0
CTM FCSM BLOCK
16-BIT UP COUNTER
IL2
IL1
IL0
IARB3
COF
EDGE
TIME BASE BUSES
IL1
INTERRUPT
CLOCK
IN
CLK1 CLK0
CLK2
OVERFLOW
BUS
CONTROL REGISTER BITS
DRVA DRVB
CONTROL REGISTER BITS
6 CLOCKS (PCLKX) FROM PRESCALER
SUBMODULE BUS
CONTROL
SELECT
DETECT
TBBA
TBBB
INPUT PIN
CTMC
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