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參數(shù)資料
| 型號： | MC68360RC25 |
| 廠商： | FREESCALE SEMICONDUCTOR INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | RISC MICROCONTROLLER, CPGA241 |
| 封裝： | PGA-241 |
| 文件頁數(shù)： | 236/962頁 |
| 文件大?。?/td> | 26435K |
| 代理商： | MC68360RC25 |
System Integration Module (SIM60)
6-66
MC68360 USER’S MANUAL
The DRAM controller does not support an external TA response
for the MC68040 burst mode. Also, for non-burst MC68040 cy-
cles, TA cannot be externally asserted before RAS is asserted.
WBT40—Wait Between Transfers (MC68EC040)
This attribute guarantees a minimum negation time for RAS when the QUICC DRAM con-
troller is used by an external MC68EC040 master. It is used to comply with the RAS pre-
charge time in DRAMs.
The user would normally decide whether to set the TSS40 bit before setting this bit.
0 = RAS is negated for 4 phases of the QUICC system clock (3 phases if
TSS40 = 1).
1 = RAS is negated for 6 phases (5 phases if TSS40 = 1).
NOTE
TSS40 affects the WBT40 value in order to gain back one of the
two phases that was lost by setting TSS40 = 1. This “gain back”
only applies to back-to-back DRAM cycles.
WBTQ—Wait Between Transfers (QUICC-Type)
This attribute guarantees a minimum negation time for RAS when the QUICC DRAM con-
troller is used by one of the internal masters or by an external master of the MC68030-
type (includes an external QUICC). It is used to comply with the RAS precharge time in
DRAMs.
0 = RAS is negated for 4 phases (3 phases in page mode—PGME = 1).
1 = RAS is negated for 6 phases (5 phases in page mode—PGME = 1).
DWQ—Delay Write for QUICC (DRAM Bank Only)
This attribute is used to add a clock to the assertion and negation of the CAS signal on
DRAM page hit write cycles. The write cycle lasts one additional clock in this case. This
attribute is applicable to an internal QUICC master and to an external MC68030/QUICC.
0 = Reads and writes are the same length.
1 = Add one clock to write cycles for DRAM banks where TCYC is set to 01.
NOTE
This bit must be set by the user if page mode is enabled for this
DRAM bank (PGME = 1), or else the DRAM may latch invalid
data during writes.
The following bits are used for SRAM bank properties:
DW40—Delay Write for 040 (SRAM Bank Only)
This attribute should be set if an additional wait state is necessary for SRAM write cycles.
This attribute is applicable only to an external MC68040 writing to a non-DRAM bank.
0 = Reads and writes are the same length.
1 = Insert one additional wait state to MC68040 write cycles to SRAM banks.
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MC68360RC25L | 功能描述:微處理器 - MPU QUICC, SIM, 4SCC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68360RC25V | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:QUad Integrated Communications Controller Users Manual |
| MC68360RC33 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:QUad Integrated Communications Controller Users Manual |
| MC68360RC33L | 功能描述:微處理器 - MPU QUICC SIM 4SCC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68360TUT | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:TUTORIAL A QUICC-START |
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