
Serial Interface with Time Slot Assigner
MC68360 USER’S MANUAL
FEx—Frame Sync Edge for TDM A or B
The L1RSYNCx and L1TSYNCx pulses are sampled with the falling/rising edge of the
channel clock according to this bit.
0 = Falling edge (Use for IDL and GCI.)
1 = Rising edge
GMx—Grant Mode for TDM A or B
0 = GCI/SCIT mode. The GCI/SCIT D channel grant mechanism for transmission is in-
ternally supported. The grant is one bit from the receive channel. This bit is marked
by programming the channel select bits of the SI RAM with 111 to assert an internal
strobe on it. Refer to 7.8.7.2.2 SCIT Programming.
1 = IDL mode. A GRANT mechanism is supported if the corresponding GR1–GR4 bits
in the SIMODE register are set. The grant is a sample of the L1GRx pin while
L1TSYNCx is asserted. This GRANT mechanism implies the IDL access controls
for transmission on the D channel. Refer to 7.8.6.2 IDL Interface Programming.
TFSDx—Transmit Frame Sync Delay for TDM A or B
These two bits determine the number of clock delays between the transmit sync and the
first bit of the transmit frame. If the CRTx bit is set (recommended with IDL or GCI), then
the transmit sync is not used, and these bits are ignored.
00 = No bit delay (The first bit of the frame is transmitted/received on the same clock
as the sync.)
01 = 1 bit delay
10 = 2 bit delay
11 = 3 bit delay
Refer to Figure 7-29 and Figure 7-30 for an example of the use of these bits.
Figure 7-29. One Clock Delay from Sync to Data (RFSD = 01)
L1CLK
END OF FRAME
L1SYNC
DATA
(FE = 1)
(CE = 0)
ONE CLOCK DELAY FROM SYNC LATCH TO FIRST BIT OF FRAME
BIT 0
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
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