
4- 28
MC68341 USER’S MANUAL
MOTOROLA
4.3.2.6 PERIODIC INTERRUPT CONTROL REGISTER (PICR). The PICR contains the
interrupt level and the vector number for the periodic interrupt request. This register can
be read or written at any time. Bits 15–11 are unimplemented and always return zero; a
write to these bits has no effect.
PICR
$022
15
14
13
12
11
10
9876543210
00000
PIRQL2 PIRQL1 PIRQL0
PIV7
PIV6
PIV5
PIV4
PIV3
PIV2
PIV1
PIV0
RESET:
0000000000001111
Supervisor Only
Bits 15–11—Reserved
PIRQL2–PIRQL0—Periodic Interrupt Request Level
These bits contain the periodic interrupt request level. Table 4-10 lists which interrupt
request level is asserted during an IACK cycle when a periodic interrupt is generated.
The periodic timer continues to run when the interrupt is disabled.
Table 4-10. PIRQL Encoding
PIRQL2
PIRQL1
PIRQL0
Interrupt Request Level
0
Periodic Interrupt Disabled
0
1
Interrupt Request Level 1
0
1
0
Interrupt Request Level 2
0
1
Interrupt Request Level 3
1
0
Interrupt Request Level 4
1
0
1
Interrupt Request Level 5
1
0
Interrupt Request Level 6
1
Interrupt Request Level 7
NOTE:
Use caution with a level 7 interrupt encoding due to the
SIM41's interrupt servicing order. See 4.2.2.7 Simultaneous
Interrupts by Sources in the SIM41 for the servicing order.
PIV7–PIV0—Periodic Interrupt Vector Bits 7–0
These bits contain the value of the vector generated during an IACK cycle in response
to an interrupt from the periodic timer. When the SIM41 responds to the IACK cycle, the
periodic interrupt vector from the PICR is placed on the bus. This vector number is
multiplied by four to form the vector offset, which is added to the vector base register to
obtain the address of the vector.
4.3.2.7 PERIODIC INTERRUPT TIMER REGISTER (PITR). The PITR contains control for
prescaling the software watchdog and periodic timer as well as the count value for the
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Freescale Semiconductor, Inc.
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