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參數(shù)資料
| 型號： | MC68332GVEH25 |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 32/88頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MCU 32BIT 25MHZ 132-PQFP |
| 標準包裝： | 36 |
| 系列： | M683xx |
| 核心處理器： | CPU32 |
| 芯體尺寸： | 32-位 |
| 速度： | 25MHz |
| 連通性： | EBI/EMI，SCI，SPI，UART/USART |
| 外圍設備： | POR，PWM，WDT |
| 輸入/輸出數(shù)： | 15 |
| 程序存儲器類型： | ROMless |
| RAM 容量： | 2K x 8 |
| 電壓 - 電源 (Vcc/Vdd)： | 4.5 V ~ 5.5 V |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 105°C |
| 封裝/外殼： | 132-BQFP 緩沖式 |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 733 (CN2011-ZH PDF) |
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MOTOROLA
MC68332
38
MC68332TS/D
The bits in this register control the function of each port F pin. Any bit cleared to zero defines the corre-
sponding pin to be an I/O pin. Any bit set to one defines the corresponding pin to be an interrupt request
signal or MODCLK. The MODCLK signal has no function after reset.
Data bus pin 9 controls the state of this register following reset. If DATA9 is set to one during reset, the
register is set to $FF, which defines all port F pins as interrupt request inputs. If DATA9 is cleared to
zero during reset, this register is set to $00, defining all port F pins as I/O pins.
3.7 Resets
Reset procedures handle system initialization and recovery from catastrophic failure. The MCU per-
forms resets with a combination of hardware and software. The system integration module determines
whether a reset is valid, asserts control signals, performs basic system configuration based on hard-
ware mode-select inputs, then passes control to the CPU.
Reset occurs when an active low logic level on the RESET pin is clocked into the SIM. Resets are gated
by the CLKOUT signal. Asynchronous resets are assumed to be catastrophic. An asynchronous reset
can occur on any clock edge. Synchronous resets are timed to occur at the end of bus cycles. If there
is no clock when RESET is asserted, reset does not occur until the clock starts. Resets are clocked in
order to allow completion of write cycles in progress at the time RESET is asserted.
Reset is the highest-priority CPU32 exception. Any processing in progress is aborted by the reset ex-
ception, and cannot be restarted. Only essential tasks are performed during reset exception processing.
Other initialization tasks must be accomplished by the exception handler routine.
3.7.1 SIM Reset Mode Selection
The logic states of certain data bus pins during reset determine SIM operating configuration. In addition,
the state of the MODCLK pin determines system clock source and the state of the BKPT pin determines
what happens during subsequent breakpoint assertions. The following table is a summary of reset
mode selection options.
PFPAR — Port F Pin Assignment Register
$YFFA1F
15
8
7
6
5
4
3
2
1
0
NOT USED
PFPA7
PFPA6
PFPA5
PFPA4
PFPA3
PFPA2
PFPA1
PFPA0
RESET:
DATA9
Table 17 Port F Pin Assignments
PFPAR Field
Port F Signal
Alternate Signal
PFPA7
PF7
IRQ7
PFPA6
PF6
IRQ6
PFPA5
PF5
IRQ5
PFPA4
PF4
IRQ4
PFPA3
PF3
IRQ3
PFPA2
PF2
IRQ2
PFPA1
PF1
IRQ1
PFPA0
PF0
MODCLK
Table 18 Reset Mode Selection
Mode Select Pin
Default Function
(Pin Left High)
Alternate Function
(Pin Pulled Low)
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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