參數(shù)資料
型號(hào)： MC68332GCFVV16
廠商： Motorola, Inc.
英文描述： 32-Bit Modular Microcontroller
中文描述： 32位微控制器模塊
文件頁數(shù)： 31/88頁
文件大?。?/td> 446K
代理商： MC68332GCFVV16
MC68332
MC68332TS/D
MOTOROLA
31
3.5.1 Chip-Select Registers
Pin assignment registers CSPAR0 and CSPAR1 determine functions of chip-select pins. These regis-
ters also determine port size (8- or 16-bit) for dynamic bus allocation.
A pin data register (PORTC) latches discrete output data.
Blocks of addresses are assigned to each chip-select function. Block sizes of 2 Kbytes to 1 Mbyte can
be selected by writing values to the appropriate base address register (CSBAR). Address blocks for
separate chip-select functions can overlap.
Chip-select option registers (CSORBT and CSOR[10:0]) determine timing of and conditions for asser-
tion of chip-select signals. Eight parameters, including operating mode, access size, synchronization,
and wait state insertion can be specified.
Initialization code often resides in a peripheral memory device controlled by the chip-select circuits. A
set of special chip-select functions and registers (CSORBT, CSBARBT) is provided to support bootstrap
operation.
3.5.2 Pin Assignment Registers
The pin assignment registers (CSPAR0 and CSPAR1) contain pairs of bits that determine the function
of chip-select pins. The pin assignment encodings used in these registers are shown below.
CSPAR0 contains seven 2-bit fields that determine the functions of corresponding chip-select pins.
CSPAR0[15:14] are not used. These bits always read zero; writes have no effect. CSPAR0 bit 1 always
reads one; writes to CSPAR0 bit 1 have no effect.
Table 12 Pin Assignment Encodings
Bit Field
00
01
10
11
Description
Discrete Output
Alternate Function
Chip Select (8-Bit Port)
Chip Select (16-Bit Port)
CSPAR0
—Chip Select Pin Assignment Register 0
$YFFA44
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
CSPA0[6]
CSPA0[5]
CSPA0[4]
CSPA0[3]
CSPA0[2]
CSPA0[1]
CSBOOT
RESET:
0
0
DATA2
1
DATA2
1
DATA2
1
DATA1
1
DATA1
1
DATA1
1
1
DATA0
Table 13 CSPAR0 Pin Assignments
CSPAR0 Field
CSPA0[6]
CSPA0[5]
CSPA0[4]
CSPA0[3]
CSPA0[2]
CSPA0[1]
CSBOOT
Chip Select Signal
CS5
CS4
CS3
CS2
CS1
CS0
CSBOOT
Alternate Signal
FC2
FC1
FC0
BGACK
BG
BR
—
Discrete Output
PC2
PC1
PC0
—
—
—
—
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