參數(shù)資料
              型號(hào): MC68332CFC20
              廠商: MOTOROLA INC
              元件分類: 微控制器/微處理器
              英文描述: 32-Bit Modular Microcontroller
              中文描述: 32-BIT, 20 MHz, MICROCONTROLLER, PQFP132
              封裝: PLASTIC, QFP-132
              文件頁數(shù): 68/88頁
              文件大小: 446K
              代理商: MC68332CFC20
              MOTOROLA
              68
              MC68332
              MC68332TS/D
              At reset, QIVR is initialized to $0F, which corresponds to the uninitialized interrupt vector in the excep-
              tion table. This vector is selected until QIVR is written. A user-defined vector ($40–$FF) should be writ-
              ten to QIVR during QSM initialization.
              After initialization, QIVR determines which two vectors in the exception vector table are to be used for
              QSM interrupts. The QSPI and SCI submodules have separate interrupt vectors adjacent to each other.
              Both submodules use the same interrupt vector with the least significant bit (LSB) determined by the
              submodule causing the interrupt.
              The value of INTV0 used during an interrupt-acknowledge cycle is supplied by the QSM. During an in-
              terrupt-acknowledge cycle, INTV[7:1] are driven on DATA[7:1] IMB lines. DATA0 is negated for an SCI
              interrupt and asserted for a QSPI interrupt. Writes to INTV0 have no meaning or effect. Reads of INTV0
              return a value of one.
              6.4.2 Pin Control Registers
              The QSM uses nine pins, eight of which form a parallel port (PORTQS) on the MCU. Although these
              pins are used by the serial subsystems, any pin can alternately be assigned as general-purpose I/O on
              a pin-by-pin basis.
              Pins used for general-purpose I/O must not be assigned to the QSPI by register PQSPAR. To avoid
              driving incorrect data, the first byte to be output must be written before DDRQS is configured. DDRQS
              must then be written to determine the direction of data flow and to output the value contained in register
              PORTQS. Subsequent data for output is written to PORTQS.
              PORTQS latches I/O data. Writes drive pins defined as outputs. Reads return data present on the pins.
              To avoid driving undefined data, first write a byte to PORTQS, then configure DDRQS.
              Clearing a bit in the PQSPAR assigns the corresponding pin to general-purpose I/O; setting a bit as-
              signs the pin to the QSPI. The PQSPAR does not affect operation of the SCI.
              QIVR
              — QSM Interrupt Vector Register
              $YFFC05
              15
              8
              7
              0
              QILR
              INTV
              RESET:
              0
              0
              0
              0
              1
              1
              1
              1
              PORTQS
              — Port QS Data Register
              $YFFC14
              15
              8
              7
              6
              5
              4
              3
              2
              1
              0
              NOT USED
              PQS7
              PQS6
              PQS5
              PQS4
              PQS3
              PQS2
              PQS1
              PQS0
              RESET:
              0
              0
              0
              0
              0
              0
              0
              0
              PQSPAR
              — PORT QS Pin Assignment Register
              DDRQS
              — PORT QS Data Direction Register
              $YFFC16
              $YFFC17
              15
              14
              13
              12
              11
              10
              9
              8
              7
              6
              5
              4
              3
              2
              1
              0
              0
              PQSPA6 PQSPA5 PQSPA4 PQSPA3
              0
              PQSPA1 PQSPA0
              DDQS7 DDQS6 DDQS5 DDQS4 DDQS3 DDQS2 DDQS1 DDQS0
              RESET:
              0
              0
              0
              0
              0
              0
              0
              0
              0
              0
              0
              0
              0
              0
              0
              0
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