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參數(shù)資料
| 型號(hào)： | MC68332AVFC20 |
| 廠(chǎng)商： | MOTOROLA INC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 32-Bit Modular Microcontroller |
| 中文描述： | 32-BIT, 20.97 MHz, MICROCONTROLLER, PQFP132 |
| 封裝： | PLASTIC, QFP-132 |
| 文件頁(yè)數(shù)： | 52/88頁(yè) |
| 文件大?。?/td> | 446K |
| 代理商： | MC68332AVFC20 |
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MOTOROLA
52
MC68332
MC68332TS/D
5 Time Processor Unit
The time processor unit (TPU) provides optimum performance in controlling time-related activity. The
TPU contains a dedicated execution unit, a tri-level prioritized scheduler, data storage RAM, dual-time
bases, and microcode ROM. The TPU controls 16 independent, orthogonal channels, each with an as-
sociated I/O pin, and is capable of performing any microcoded time function. Each channel contains
dedicated hardware that allows input or output events to occur simultaneously on all channels.
Figure 12 TPU Block Diagram
5.1 MC68332 and MC68332A Time Functions
The following paragraphs describe factory-programmed time functions implemented in standard and
enhanced standard TPU microcode ROM. A complete description of the functions is beyond the scope
of this summary. Refer to Using the TPU Function Library and TPU Emulation Mode(TPUPN00/D) as
well as other TPU programming notes for more information about specific functions.
5.1.1 Discrete Input/Output (DIO)
When a pin is used as a discrete input, a parameter indicates the current input level and the previous
15 levels of a pin. Bit 15, the most significant bit of the parameter, indicates the most recent state. Bit
14 indicates the next most recent state, and so on. The programmer can choose one of the three fol-
lowing conditions to update the parameter: 1) when a transition occurs, 2) when the CPU makes a re-
quest, or 3) when a rate specified in another parameter is matched. When a pin is used as a discrete
output, it is set high or low only upon request by the CPU.
T2CLK
PINS
SERVICE REQUESTS
DATA
TCR1
TCR2
MICROENGINE
CONTROL
STORE
EXECUTION
UNIT
I M B
PARAMETER
RAM
CHANNEL
CONTROL
DEVELOPMENT
SUPPORT AND TEST
SYSTEM
CONFIGURATION
SCHEDULER
CONTROL AND DATA
CONTROL
TIMER
CHANNELS
CHANNEL 0
CHANNEL 1
CHANNEL 15
C
DATA
TPU BLOCK
HOST
INTERFACE
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