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    參數資料
    型號: MC68332AVFC16
    廠商: MOTOROLA INC
    元件分類: 微控制器/微處理器
    英文描述: 32-Bit Modular Microcontroller
    中文描述: 32-BIT, 16.78 MHz, MICROCONTROLLER, PQFP132
    封裝: PLASTIC, QFP-132
    文件頁數: 85/88頁
    文件大?。?/td> 446K
    代理商: MC68332AVFC16
    MC68332
    MC68332TS/D
    MOTOROLA
    85
    RASP — RAM Array Space Field
    0 = TPURAM array is placed in unrestricted space
    1 = TPURAM array is placed in supervisor space
    TRAMTST
    — TPURAM Test Register
    TRAMTST is used for factory testing of the TPURAM module.
    $YFFB02
    ADDR[23:11] — RAM Array Base Address
    These bits specify address lines ADDR[23:11] of the base address of the RAM array when enabled.
    RAMDS — RAM Array Disable
    0 = RAM array is enabled
    1 = RAM array is disabled
    The RAM array is disabled by internal logic after a master reset. Writing a valid base address to the
    RAM array base address field (bits [15:3]) automatically clears RAMDS, enabling the RAM array.
    7.4 TPURAM Operation
    There are six TPURAM operating modes, as follows:
    1.
    The TPURAM module is in normal mode when powered by V
    DD
    . The array can be accessed
    by byte, word, or long word. A byte or aligned word (high-order byte is at an even address) ac-
    cess only takes one bus cycle or two system clocks. A long word or misaligned word access
    requires two bus cycles.
    Standby mode is intended to preserve TPURAM contents when V
    DD
    is removed. TPURAM
    contents are maintained by V
    STBY
    . Circuitry within the TPURAM module switches to the higher
    of V
    DD
    or V
    STBY
    with no loss of data. When TPURAM is powered by V
    STBY
    , access to the array
    is not guaranteed.
    Reset mode allows the CPU to complete the current bus cycle before resetting. When a syn-
    chronous reset occurs while a byte or word TPURAM access is in progress, the access will be
    completed. If reset occurs during the first word access of a long-word operation, only the first
    word access will be completed. If reset occurs during the second word access of a long word
    operation, the entire access will be completed. Data being read from or written to the RAM may
    be corrupted by asynchronous reset.
    Test mode functions in conjunction with the SIM test functions. Test mode is used during factory
    test of the MCU.
    Writing the STOP bit of TRAMMCR causes the TPURAM module to enter stop mode. The
    TPURAM array is disabled (which allows external logic to decode TPURAM addresses, if nec-
    essary), but all data is retained. If V
    DD
    falls below V
    STBY
    during stop mode, internal circuitry
    switches to V
    STBY
    , as in standby mode. Stop mode is exited by clearing the STOP bit.
    The TPURAM array may be used to emulate the microcode ROM in the TPU module. This pro-
    vides a means of developing custom TPU code. The TPU selects TPU emulation mode. While
    in TPU emulation mode, the access timing of the TPURAM module matches the timing of the
    TPU microinstruction ROM to ensure accurate emulation. Normal accesses via the IMB are in-
    hibited and the control registers have no effect, allowing external RAM to emulate the TPURAM
    at the same addresses.
    2.
    3.
    4.
    5.
    6.
    TRAMBAR
    — TPURAM Base Address and Status Register
    $YFFB04
    15
    14
    13
    12
    11
    10
    9
    8
    7
    6
    5
    4
    3
    2
    1
    0
    ADDR
    23
    ADDR
    22
    ADDR
    21
    ADDR
    20
    ADDR
    19
    ADDR
    18
    ADDR
    17
    ADDR
    16
    ADDR
    15
    ADDR
    14
    ADDR
    13
    ADDR
    12
    ADDR
    11
    NOT USED
    RAMDS
    RESET:
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
    0
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