參數(shù)資料
型號(hào)： MC68332
廠商： Motorola, Inc.
英文描述： 32-Bit Modular Microcontroller
中文描述： 32位微控制器模塊
文件頁(yè)數(shù)： 21/88頁(yè)
文件大?。?/td> 446K
代理商： MC68332
MC68332
MC68332TS/D
MOTOROLA
21
3.2.3 Bus Monitor
The internal bus monitor checks for excessively long DSACK response times during normal bus cycles
and for excessively long DSACK or AVEC response times during interrupt acknowledge cycles. The
monitor asserts BERR if response time is excessive.
DSACK and AVEC response times are measured in clock cycles. The maximum allowable response
time can be selected by setting the BMT field.
The monitor does not check DSACK response on the external bus unless the CPU initiates the bus cy-
cle. The BME bit in the SYPCR enables the internal bus monitor for internal to external bus cycles. If a
system contains external bus masters, an external bus monitor must be implemented and the internal
to external bus monitor option must be disabled.
3.2.4 Halt Monitor
The halt monitor responds to an assertion of HALT on the internal bus. A flag in the reset status register
(RSR) indicates that the last reset was caused by the halt monitor. The halt monitor reset can be inhib-
ited by the HME bit in the SYPCR.
3.2.5 Spurious Interrupt Monitor
The spurious interrupt monitor issues BERR if no interrupt arbitration occurs during an interrupt-ac-
knowledge cycle.
3.2.6 Software Watchdog
The software watchdog is controlled by SWE in the SYPCR. Once enabled, the watchdog requires that
a service sequence be written to SWSR on a periodic basis. If servicing does not take place, the watch-
dog times out and issues a reset. This register can be written at any time, but returns zeros when read.
Register shown with read value
Perform a software watchdog service sequence as follows:
a.
b.
Write $55 to SWSR.
Write $AA to SWSR.
Both writes must occur before time-out in the order listed, but any number of instructions can be exe-
cuted between the two writes.
The watchdog clock rate is affected by SWP and SWT in SYPCR. When SWT[1:0] are modified, a
watchdog service sequence must be performed before the new time-out period takes effect.
The reset value of SWP is affected by the state of the MODCLK pin on the rising edge of reset, as shown
in the following table.
SWSR
—Software Service Register
$YFFA27
15
8
7
6
5
4
3
2
1
0
NOT USED
0
0
0
0
0
0
0
0
RESET:
0
0
0
0
0
0
0
0
MODCLK
0
1
SWP
1
0
相關(guān)PDF資料
PDF描述
MC68332ACFC16 32-Bit Modular Microcontroller
MC68332ACFC20 32-Bit Modular Microcontroller
MC68332ACFV16 32-Bit Modular Microcontroller
MC68332ACFV20 32-Bit Modular Microcontroller
MC68332AMFC16 32-Bit Modular Microcontroller
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MC683326CFC16 制造商:Motorola Inc 功能描述:
MC68332ACAG16 功能描述:32位微控制器 - MCU 32B MCU 2KRAM TPU QSM RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:90 MHz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT
MC68332ACAG16 制造商:Freescale Semiconductor 功能描述:32-Bit Microcontroller IC
MC68332ACAG16B1 制造商:Freescale Semiconductor 功能描述:
MC68332ACAG20 功能描述:32位微控制器 - MCU 32B MCU 2KRAM TPU QSM RoHS:否 制造商:Texas Instruments 核心:C28x 處理器系列:TMS320F28x 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:90 MHz 程序存儲(chǔ)器大小:64 KB 數(shù)據(jù) RAM 大小:26 KB 片上 ADC:Yes 工作電源電壓:2.97 V to 3.63 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:LQFP-80 安裝風(fēng)格:SMD/SMT
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