MOTOROLA
A-10
ELECTRICAL CHARACTERISTICS
MC68331
USER’S MANUAL
A
14
14A
14B
15
16
17
18
20
21
22
23
24
25
26
27
27A
28
29
29A
30
30A
31
33
35
37
39
39A
46
46A
47A
AS, CS Width Asserted
DS, CS Width Asserted (Write)
AS, CS Width Asserted (Fast Write Cycle)
AS, DS, CS Width Negated
6
Clock High to AS, DS, R/W High Impedance
AS, DS, CS Negated to R/W Negated
Clock High to R/W High
Clock High to R/W Low
R/W Asserted to AS, CS Asserted
R/W Low to DS, CS Asserted (Write)
Clock High to Data Out Valid
Data Out Valid to Negating Edge of AS, CS
DS, CS Negated to Data Out Invalid (Data Out Hold)
Data Out Valid to DS, CS Asserted (Write)
Data In Valid to Clock Low (Data Setup)
Late BERR, HALT Asserted to Clock Low (Setup Time)
AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated
DS, CS Negated to Data In Invalid (Data In Hold)
7
DS, CS Negated to Data In High Impedance
7, 8
CLKOUT Low to Data In Invalid (Fast Cycle Hold)
7
CLKOUT Low to Data In High Impedance
7
DSACK[1:0] Asserted to Data In Valid
9
Clock Low to BG Asserted/Negated
BR Asserted to BG Asserted (RMC Not Asserted)
10
BGACK Asserted to BG Negated
BG Width Negated
BG Width Asserted
R/W Width Asserted (Write or Read)
R/W Width Asserted (Fast Write or Read Cycle)
Asynchronous Input Setup Time
BR, BGACK, DSACK[1:0], BERR, AVEC, HALT
Asynchronous Input Hold Time
DSACK[1:0] Asserted to BERR, HALT Asserted
11
Data Out Hold from Clock High
Clock High to Data Out High Impedance
R/W Asserted to Data Bus Impedance Change
RESET Pulse Width (Reset Instruction)
BERR Negated to HALT Negated (Rerun)
Clock Low to Data Bus Driven (Show)
Data Setup Time to Clock Low (Show)
Data Hold from Clock Low (Show)
BKPT Input Setup Time
BKPT Input Hold Time
Mode Select Setup Time
Mode Select Hold Time
RESET Assertion Time
12
RESET Rise Time
13,14
t
SWA
t
SWAW
t
SWDW
t
SN
t
CHSZ
t
SNRN
t
CHRH
t
CHRL
t
RAAA
t
RASA
t
CHDO
t
DVASN
t
SNDOI
t
DVSA
t
DICL
t
BELCL
t
SNDN
t
SNDI
t
SHDI
t
CLDI
t
CLDH
t
DADI
t
CLBAN
t
BRAGA
t
GAGN
t
GH
t
GA
t
RWA
t
RWAS
t
AIST
80
36
32
32
—
10
0
0
10
54
—
10
10
10
5
15
0
0
—
10
—
—
—
1
1
2
1
115
70
5
—
—
—
—
47
—
23
23
—
—
23
—
—
—
—
—
60
—
48
—
72
46
23
—
2
—
—
—
—
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
cyc
t
cyc
t
cyc
t
cyc
ns
ns
ns
47B
48
53
54
55
56
57
70
71
72
73
74
75
76
77
78
t
AIHT
t
DABA
t
DOCH
t
CHDH
t
RADC
t
HRPW
t
BNHN
t
SCLDD
t
SCLDS
t
SCLDH
t
BKST
t
BKHT
t
MSS
t
MSH
t
RSTA
t
RSTR
12
—
0
—
32
512
0
0
10
10
10
10
20
0
4
—
—
30
—
23
—
—
—
23
—
—
—
—
—
—
—
10
ns
ns
ns
ns
ns
t
cyc
ns
ns
ns
ns
ns
ns
t
cyc
ns
t
cyc
t
cyc
Table A-6a 20.97 MHz AC Timing, (Continued)
(V
DD
and V
DDSYN
= 5.0 Vdc
±
5%, V
SS
= 0 Vdc, T
A
= T
L
to T
H
)
Num
Characteristic
Symbol
Min
Max
Unit