MOTOROLA
A-8
ELECTRICAL CHARACTERISTICS
MC68331
USER’S MANUAL
A
Table A-6 16.78 MHz AC Timing
(V
DD
and V
DDSYN
= 5.0 Vdc
±
10%, V
SS
= 0 Vdc, T
A
= T
L
to T
H
)
Num
F1
1
1A
1B
2, 3
2A, 3A ECLK Pulse Width
2B, 3B External Clock Input High/Low Time
3
4, 5
Clock Rise and Fall Time
4A, 5A Rise and Fall Time — All Outputs except CLKOUT
4B, 5B External Clock Rise and Fall Time
4
6
Clock High to Address, FC, SIZE, RMC Valid
7
Clock High to Address, Data, FC, SIZE, RMC High Impedance
8
Clock High to Address, FC, SIZE, RMC Invalid
9
Clock Low to AS, DS, CS Asserted
9A
AS to DS or CS Asserted (Read)
5
9C
Clock Low to IFETCH, IPIPE Asserted
11
Address, FC, SIZE, RMC Valid
to AS, CS Asserted
12
Clock Low to AS, DS, CS Negated
12A
Clock Low to IFETCH, IPIPE Negated
13
AS, DS, CS Negated to
Address, FC, SIZE Invalid (Address Hold)
14
AS, CS Width Asserted
14A
DS, CS Width Asserted (Write)
14B
AS, CS Width Asserted (Fast Write Cycle)
15
AS, DS, CS Width Negated
6
16
Clock High to AS, DS, R/W High Impedance
17
AS, DS, CS Negated to R/W Negated
18
Clock High to R/W High
20
Clock High to R/W Low
21
R/W Asserted to AS, CS Asserted
22
R/W Low to DS, CS Asserted (Write)
23
Clock High to Data Out Valid
24
Data Out Valid to Negating Edge of AS, CS
25
DS, CS Negated to Data Out Invalid (Data Out Hold)
26
Data Out Valid to DS, CS Asserted (Write)
27
Data In Valid to Clock Low (Data Setup)
27A
Late BERR, HALT Asserted to Clock Low (Setup Time)
28
AS, DS Negated to DSACK[1:0], BERR, HALT, AVEC Negated
29
DS, CS Negated to Data In Invalid (Data In Hold)
7
29A
DS, CS Negated to Data In High Impedance
7, 8
30
CLKOUT Low to Data In Invalid (Fast Cycle Hold)
7
30A
CLKOUT Low to Data In High Impedance
7
31
DSACK[1:0] Asserted to Data In Valid
9
33
Clock Low to BG Asserted/Negated
35
BR Asserted to BG Asserted (RMC Not Asserted)
10
37
BGACK Asserted to BG Negated
Characteristic
Symbol
f
t
cyc
t
Ecyc
t
Xcyc
t
CW
t
ECW
t
XCHL
t
Crf
t
rf
t
XCrf
t
CHAV
t
CHAZx
t
CHAZn
t
CLSA
t
STSA
t
CLIA
t
AVSA
Min
0.13
59.6
476
59.6
24
236
29.8
—
—
—
0
0
0
2
–15
2
15
Max
16.78
—
—
—
—
—
—
5
8
5
29
59
—
25
15
22
—
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Frequency of Operation (32.768 kHz crystal)
2
Clock Period
ECLK Period
External Clock Input Period
3
Clock Pulse Width
t
CLSN
t
CLIN
t
SNAI
2
2
15
29
22
—
ns
ns
ns
t
SWA
t
SWAW
t
SWDW
t
SN
t
CHSZ
t
SNRN
t
CHRH
t
CHRL
t
RAAA
t
RASA
t
CHDO
t
DVASN
t
SNDOI
t
DVSA
t
DICL
t
BELCL
t
SNDN
t
SNDI
t
SHDI
t
CLDI
t
CLDH
t
DADI
t
CLBAN
t
BRAGA
t
GAGN
100
45
40
40
—
15
0
0
15
70
—
15
15
15
5
20
0
0
—
15
—
—
—
1
1
—
—
—
—
59
—
29
29
—
—
29
—
—
—
—
—
80
—
55
—
90
50
29
—
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
cyc
t
cyc