MC68331
USER’S MANUAL
MOTOROLA
v
TABLE OF CONTENTS
(Continued)
Title
Paragraph
Page
4.5.6.1
4.5.6.2
4.6
4.6.1
4.6.2
4.6.3
4.6.3.1
4.6.3.2
4.6.3.3
4.6.4
4.6.5
4.6.5.1
4.6.5.2
4.6.6
4.6.7
4.6.8
4.6.9
4.7
4.7.1
4.7.2
4.7.3
4.7.4
4.7.5
4.8
4.8.1
4.8.1.1
4.8.1.2
4.8.1.3
4.8.1.4
4.8.2
4.8.3
4.8.4
4.9
4.9.1
4.9.2
4.9.3
4.10
Slave (Factory Test) Mode Arbitration ......................................... 4-35
Show Cycles ................................................................................ 4-35
Reset ............................................................................................................4-36
Reset Exception Processing ................................................................4-36
Reset Control Logic ..............................................................................4-37
Reset Mode Selection ..........................................................................4-37
Data Bus Mode Selection ............................................................. 4-38
Clock Mode Selection .................................................................. 4-40
Breakpoint Mode Selection .......................................................... 4-40
MCU Module Pin Function During Reset .............................................4-40
Pin State During Reset .........................................................................4-41
Reset States of SIM Pins ............................................................. 4-41
Reset States of Pins Assigned to Other MCU Modules ............... 4-42
Reset Timing ........................................................................................4-42
Power-On Reset ...................................................................................4-43
Reset Processing Summary .................................................................4-44
Reset Status Register ..........................................................................4-45
Interrupts ......................................................................................................4-45
Interrupt Exception Processing ............................................................4-45
Interrupt Priority and Recognition .........................................................4-45
Interrupt Acknowledge and Arbitration .................................................4-46
Interrupt Processing Summary .............................................................4-47
Interrupt Acknowledge Bus Cycles .......................................................4-48
Chip Selects .................................................................................................4-48
Chip-Select Registers ...........................................................................4-50
Chip-Select Pin Assignment Registers ........................................ 4-51
Chip-Select Base Address Registers ........................................... 4-52
Chip-Select Option Registers ....................................................... 4-52
PORTC Data Register .................................................................. 4-54
Chip-Select Operation ..........................................................................4-54
Using Chip-Select Signals for Interrupt Acknowledge ..........................4-54
Chip-Select Reset Operation ................................................................4-55
Parallel Input/Output Ports ...........................................................................4-57
Pin Assignment Registers ....................................................................4-57
Data Direction Registers ......................................................................4-57
Data Registers ......................................................................................4-57
Factory Test .................................................................................................4-57
SECTION 5 CENTRAL PROCESSING UNIT
5.1
5.2
General ...........................................................................................................5-1
CPU32 Registers ............................................................................................5-2