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參數(shù)資料
| 型號(hào)： | MC68307PU16V |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 16-BIT, 16.67 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁(yè)數(shù)： | 8/264頁(yè) |
| 文件大?。?/td> | 949K |
| 代理商： | MC68307PU16V |
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System Integration Module
5-10
MC68307 USER’S MANUAL
MOTOROLA
default state of BUSW0 reflects the value of the BUSW external pin (0 = 8-bit data bus, 1 =
16-bit data bus), and the default state of the other BUSWx bits is for a 16-bit port size.
When the data-bus sizing logic is used to configure a chip select as an 8-bit port select, any
16-bit bus cycles from the processor appears on the external pins as two 8-bit read or write
cycles with normal M68000 timings on all signals and the addition of a valid A0 signal. D15–
D8 is always used for bus cycles of this kind.
NOTE
If byte operations are performed where 8-bit bus mode is used,
there is no difference in throughput compared to 16-bit bus
mode. However, if 32-bit long word or 16-bit word operations are
used over the 8-bit data bus (including all instruction fetches),
the performance is exactly half that of the equivalent speed 16-
bit-wide data bus.
5.1.3.2 8051-COMPATIBLE BUS INTERFACE. The
8051-compatible
bus
interface
contains logic to multiplex the low eight address lines (A7–A0) and the low eight data lines
(D7–D0) onto the same pins. CS3 is used to select the memory area assigned to the 8051-
compatible bus, it controls the external bus interface logic, triggering the address latch
enable signal, and gating the RD and WR signals. Refer to Section 5.1.2 Chip Select and
Wait-State Logic and Section 5.2.2 Chip Select Registers for details of how to configure
the chip select logic for this interface. Also refer to Section 5.2.1 System Configuration
and Protection Registers for details of how to configure the MC68307 pins for the 8051-
compatible bus.
The 8051-compatible interface uses the same 8-bit data bus sizing scheme as offered with
the M68000 chip selects. As such, there is no restriction on the data operations which can
be used—both byte, word and long transfers can be initiated by the processor to an 8051-
compatible device which can have contiguous byte locations.
5.1.3.3 PORT A, PORT B GENERAL-PURPOSE I/O PORTS. The MC68307 supports two
general purpose I/O ports, port A and port B, whose pins can be configured as general-
purpose input/output pins or dedicated peripheral interface pins for the on-chip modules
(UART, M-bus, timer, interrupts, peripheral chip selects). Port A is an 8-bit I/O port. Port B
is a 16-bit I/O port.
Each of the 8 port A and 16 port B pins are independently configured as a general-purpose
I/O pin if the corresponding bit in the port A or B control register (PACNT, PBCNT) is cleared.
Port pins are configured as dedicated on-chip peripheral pins if the corresponding PACNT
or PBCNT bit is set. Refer to Section 5.2.3 External Bus Interface Control Registers for
details of programming the general-purpose ports.
For each port pin, when acting as a general-purpose I/O pin, the signal direction for that pin
is determined by the corresponding control bit in the port A or B data direction register
(PADDR, PBDDR). The port I/O pin is configured as an input if the corresponding PADDR
or PBDDR bit is cleared; it is configured as an output if the corresponding PADDR or
PBDDR bit is set. All PADDR, PBDDR, PACNT, and PBCNT bits are cleared on cold reset,
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相關(guān)代理商/技術(shù)參數(shù) |
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| MC68307UM | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Technical Summary Integrated Multiple-Bus Processor |
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| MC68322FT20 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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