MOTOROLA
MC68306 PRODUCT INFORMATION
5
EC000 CORE PROCESSOR
The core processor is the heart of an integrated processor; it supervises system functions, makes decisions,
manipulates data, and directs I/O. The EC000 core is a core implementation of the MC68000 32-bit
microprocessor architecture. The programmer can use any of the eight 32-bit data registers for fast
manipulation of data and any of the eight 32-bit address registers for indexing data in memory. Flexible
instructions support data movement, arithmetic functions, logical operations, shifts and rotates, bit set and
clear, conditional and unconditional program branches, and overall system control.
The EC000 core can operate on data types of single bits, binary-coded decimal (BCD) digits, and 8, 16, and
32 bits. The integrated chip selects allow peripherals and data in memory to reside anywhere in the 4-Gbyte
linear address space. A supervisor operating mode protects system-level resources from the more restricted
user mode, allowing a true virtual environment to be developed. Many addressing modes complement these
instructions, including predecrement and postincrement, which allow simple stack and queue maintenance
and scaled indexing for efficient table accesses. Data types and addressing modes are supported
orthogonally by all data operations and with all appropriate addressing modes. Position-independent code is
easily written.
Like all M68000 family processors, the EC000 core recognizes interrupts of seven different priority levels
and allows the peripheral to vector the processor to the desired service routine. Internal trap exceptions
ensure proper instruction execution with good addresses and data, allow operating system intervention in
special situations, and permit instruction tracing. Hardware signals can either terminate or rerun bad
memory accesses before instructions process data incorrectly. The EC000 core provides 2.4 MIPS at 16.67
MHz.
ON-CHIP PERIPHERALS
To improve total system throughput and reduce part count, board size, and cost of system implementation,
the M68300 family integrates on-chip, intelligent peripheral modules and typical glue logic. The functions on
the MC68306 include two serial channels, a DRAM controller, a parallel port, and system glue logic.
68681 MODULE
Most digital systems use serial I/O to communicate with host computers, operator terminals, or remote
devices. The MC68306 contains a two-channel, full-duplex UART with an integrated timer. An on-chip baud
rate generator provides standard baud rates up the 38.4K baud to each channel's receiver and transmitter.
The 68681 module is identical to the MC68681/MC2681 DUART.
Each communication channel is completely independent. Data formats can be 5, 6, 7, or 8 bits with even,
odd, or no parity and stop bits up to 2 in 1/16 increments. Four-byte receive buffers and two-byte transmit
buffers minimize CPU service calls. Each channel provides a wide variety of error detection and maskable
interrupt capability. Full-duplex, autoecho loopback, local loopback, and remote loopback modes can be
selected. Multidrop applications are also supported.
A 3.6864-MHz crystal drives the baud rate generators. Each transmit and receive channel can be
programmed for a different baud rate. Full modem support is provided with separate request-to-send (RTS)
and clear-to-send (CTS) signals for each channel.
The integrated 16-bit timer/counter can operate in a counter mode or a timer mode. The timer/counter can
function as a system stopwatch, a real-time single interrupt generator, or a device watchdog when in counter
mode. In timer mode, the timer/counter can be used as a programmable clock source for channels A and B,
a periodic interrupt generator, or a variable duty cycle square-wave generator.
F
re
e
sc
a
le
S
e
m
ic
o
n
d
u
c
to
r,
I
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
c
..
.