MOTOROLA
M68040 USER’S MANUAL
ix
TABLE OF CONTENTS (Continued)
Paragraph
Page
Number
Title
Number
5.4.2
Transfer in Progress (TIP) ................................................................. 5-8
5.4.3
Transfer Acknowledge (TA) ...............................................................5-8
5.4.4
Transfer Error Acknowledge (TEA) .................................................... 5-8
5.4.5
Transfer Cache Inhibit (TCI) .............................................................. 5-9
5.4.6
Transfer Burst Inhibit (TBI) ................................................................. 5-9
5.5
Snoop Control Signals...........................................................................5-9
5.5.1
Snoop Control (SC1, SC0) ................................................................ 5-9
5.5.2
Memory Inhibit (MI)............................................................................ 5-9
5.6
Arbitration Signals .................................................................................5-10
5.6.1
Bus Request (BR) ..............................................................................5-10
5.6.2
Bus Grant (BG) .................................................................................. 5-10
5.6.3
Bus Busy (BB)....................................................................................5-10
5.7
Processor Control Signals .....................................................................5-10
5.7.1
Cache Disable (CDIS)........................................................................ 5-10
5.7.2
Reset In (RSTI) .................................................................................. 5-11
5.7.3
Reset Out (RSTO)..............................................................................5-11
5.8
Interrupt Control Signals........................................................................5-11
5.8.1
Interrupt Priority Level (IPL2–IPL0).................................................... 5-11
5.8.2
Interrupt Pending Status (IPEND) ......................................................5-12
5.8.3
Autovector (AVEC) ............................................................................. 5-12
5.9
Status And Clock Signals ......................................................................5-12
5.9.1
Processor Status (PST3–PST0) ........................................................5-12
5.9.2
Bus Clock (BCLK) ..............................................................................5-14
5.9.3
Processor Clock (PCLK)—Not on MC68040V and MC68EC040V ... 5-14
5.10
MMU Disable (MDIS)—Not on MC68EC040 .........................................5-14
5.11
Data Latch Enable (DLE)—Only on MC68040...................................... 5-14
5.12
Test Signals ..........................................................................................5-15
5.12.1
Test Clock (TCK) ...............................................................................5-15
5.12.2
Test Mode Select (TMS) ....................................................................5-15
5.12.3
Test Data In (TDI) ..............................................................................5-15
5.12.4
Test Data Out (TDO) ......................................................................... 5-15
5.12.5
Test Reset (TRST)—Not on MC68040V and MC68EC040V............. 5-15
5.13
Power Supply Connections ................................................................... 5-15
5.14
Signal Summary ....................................................................................5-16
Section 6
IEEE 1149.1 Test Access Port (JTAG)
6.1
Overview ............................................................................................... 6-2
6.2
Instruction Shift Register .......................................................................6-3
6.2.1
EXTEST .............................................................................................6-3
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Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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