MOTOROLA
M68040 USER’S MANUAL
vii
TABLE OF CONTENTS (Continued)
Paragraph
Page
Number
Title
Number
Section 3
Memory Management Unit
(Except MC68EC040 and MC68EC040V)
3.1
Memory Management Programming Model ..........................................3-3
3.1.1
User and Supervisor Root Pointer Registers..................................... 3-3
3.1.2
Translation Control Register ..............................................................3-4
3.1.3
Transparent Translation Registers .................................................... 3-5
3.1.4
MMU Status Register ........................................................................3-6
3.2
Logical Address Translation ..................................................................3-7
3.2.1
Translation Tables .............................................................................3-7
3.2.2
Descriptors ........................................................................................3-12
3.2.2.1
Table Descriptors ...........................................................................3-12
3.2.2.2
Page Descriptors ...........................................................................3-13
3.2.2.3
Descriptor Field Definitions ............................................................3-13
3.2.3
Translation Table Example ................................................................3-16
3.2.4
Variations in Translation Table Structure ..........................................3-16
3.2.4.1
Indirect Action ................................................................................ 3-16
3.2.4.2
Table Sharing Between Tasks ....................................................... 3-18
3.2.4.3
Table Paging ..................................................................................3-19
3.2.4.4
Dynamically Allocated Tables ........................................................3-21
3.2.5
Table Search Accesses .....................................................................3-21
3.2.6
Address Translation Protection .........................................................3-23
3.2.6.1
Supervisor and User Translation Tables........................................ 3-23
3.2.6.2
Supervisor Only..............................................................................3-23
3.2.6.3
Write Protect .................................................................................. 3-24
3.3
Address Translation Caches .................................................................3-26
3.4
Transparent Translation ........................................................................3-29
3.5
Address Translation Summary ..............................................................3-30
3.6
MMU Effect on RSTI and MDIS ............................................................. 3-31
3.6.1
Effect of RSTI on the MMUs ..............................................................3-31
3.6.2
Effect of MDIS on Address Translation .............................................. 3-31
3.7
MMU Instructions .................................................................................. 3-33
3.7.1
MOVEC .............................................................................................3-33
3.7.2
PFLUSH.............................................................................................3-33
3.7.3
PTEST ............................................................................................... 3-33
3.7.4
Register Programming Considerations.............................................. 3-34
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Freescale Semiconductor, Inc.
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