參數(shù)資料
型號: MC56F8355MFGE
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號處理
英文描述: 4-BIT, 120 MHz, OTHER DSP, PQFP128
封裝: ROHS COMPLIANT, PLASTIC, LQFP-128
文件頁數(shù): 15/172頁
文件大小: 844K
代理商: MC56F8355MFGE
Register Descriptions
56F8355 Technical Data, Rev. 17
Freescale Semiconductor
111
Preliminary
Table 2-2 to identify which pins can deactivate the internal pullup resistor.
Figure 6-8 SIM Pullup Disable Register (SIM_PUDR)
6.5.6.1
Reserved—Bit 15
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.6.2
PWMA1—Bit 14
This bit controls the pullup resistors on the FAULTA3 pin.
6.5.6.3
CAN—Bit 13
This bit controls the pullup resistors on the CAN_RX pin.
6.5.6.4
EMI_MODE—Bit 12
This bit controls the pullup resistors on the EMI_MODE pin
Note:
In this package, this input pin is double-bonded with the adjacent VSS pin and this bit should be
changed to a 1 in order to reduce power consumption.
6.5.6.5
RESET—Bit 11
This bit controls the pullup resistors on the RESET pin.
6.5.6.6
IRQ—Bit 10
This bit controls the pullup resistors on the IRQA and IRQB pins.
6.5.6.7
XBOOT—Bit 9
This bit controls the pullup resistors on the EXTBOOT pin.
Note:
In this package, this input pin is double-bonded with the adjacent VSS pin and this bit should be
changed to a 1 in order to reduce power consumption.
6.5.6.8
PWMB—Bit 8
This bit controls the pullup resistors on the FAULTB0, FAULTB1, FAULTB2, and FAULTB3 pins.
6.5.6.9
PWMA0—Bit 7
This bit controls the pullup resistors on the FAULTA0, FAULTA1, and FAULTA2 pins.
Base + $8
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
PWMA1
CAN
EMI_
MODE
RESET
IRQ
XBOOT
PWMB
PWMA0
0
CTRL
0
JTAG
00
0
Write
RESET
00
0
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