參數(shù)資料
型號: MC56F8347MPYE
廠商: Freescale Semiconductor
文件頁數(shù): 87/172頁
文件大?。?/td> 0K
描述: IC DIGITAL SIGNAL CTLR 160-LQFP
標(biāo)準(zhǔn)包裝: 40
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 60MHz
連通性: CAN,EBI/EMI,SCI,SPI
外圍設(shè)備: POR,PWM,溫度傳感器,WDT
輸入/輸出數(shù): 76
程序存儲器容量: 136KB(68K x 16)
程序存儲器類型: 閃存
RAM 容量: 6K x 16
電壓 - 電源 (Vcc/Vdd): 2.25 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 外部
工作溫度: -40°C ~ 125°C
封裝/外殼: 160-LQFP
包裝: 托盤
配用: MC56F8367EVME-ND - EVAL BOARD FOR MC56F83X
Signal Pins
56F8347 Technical Data, Rev.11
Freescale Semiconductor
21
Preliminary
A6
(GPIOE2)
17
G1
Output
Schmitt
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
Address Bus — A6 - A7 specify two of the address lines for
external program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus
control register (BCR), A6 - A7 and EMI control signals are
tri-stated when the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1
instead of using the default setting.
Port E GPIO — These two GPIO pins can be individually
programmed as input or output pins.
After reset, the default state is Address Bus.
To deactivate the internal pull-up resistor, clear the
appropriate GPIO bit in the GPIOE_PUR register.
Example: GPIOE2, clear bit 2 in the GPIOE_PUR register.
A7
(GPIOE3)
18
G3
A8
(GPIOA0)
19
G2
Output
Schmitt
Input/
Output
In reset,
output is
disabled,
pull-up is
enabled
Address Bus— A8 - A15 specify eight of the address lines
for external program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus
control register (BCR), A8 - A15 and EMI control signals are
tri-stated when the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1
instead of using the default setting.
Port A GPIO — These eight GPIO pins can be individually
programmed as input or output pins.
After reset, the default state is Address Bus.
To deactivate the internal pull-up resistor, clear the
appropriate GPIO bit in the GPIOA_PUR register.
Example: GPIOA0, clear bit 0 in the GPIOA_PUR register.
A9
(GPIOA1)
20
H1
A10
(GPIOA2)
21
H2
A11
(GPIOA3)
22
H4
A12
(GPIOA4)
23
H3
A13
(GPIOA5)
24
J1
A14
(GPIOA6)
25
J2
A15
(GPIOA7)
26
J3
Table 2-2 Signal and Package Information for the 160-Pin LQFP and MBGA (Continued)
Signal Name
Pin
No.
Ball
No.
Type
State
During
Reset
Signal Description
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