參數(shù)資料
型號(hào): MC56F8347MPY60
廠商: FREESCALE SEMICONDUCTOR INC
元件分類: 數(shù)字信號(hào)處理
英文描述: 16-BIT, 120 MHz, OTHER DSP, PQFP160
封裝: LQFP-160
文件頁數(shù): 87/172頁
文件大小: 2202K
代理商: MC56F8347MPY60
Signal Pins
56F8347 Technical Data, Rev. 5.0
Freescale Semiconductor
21
Preliminary
A6
(GPIOE2)
17
Output
Schmitt
Input/
Output
Tri-stated
Input
Address Bus — A6 - A7 specify two of the address lines for
external program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), A6 - A7 and EMI control signals are tri-stated
when the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1
instead of using the default setting.
Port E GPIO — These two GPIO pins can be individually
programmed as input or output pins.
After reset, the default state is Address Bus.
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOE_PUR register.
Example: GPIOE2, clear bit 2 in the GPIOE_PUR register.
A7
(GPIOE3)
18
A8
(GPIOA0)
19
Output
Schmitt
Input/
Output
Tri-stated
Input
Address Bus— A8 - A15 specify eight of the address lines for
external program or data memory accesses.
Depending upon the state of the DRV bit in the EMI bus control
register (BCR), A8 - A15 and EMI control signals are tri-stated
when the external bus is inactive.
Most designs will want to change the DRV state to DRV = 1
instead of using the default setting.
Port A GPIO — These eight GPIO pins can be individually
programmed as input or output pins.
After reset, the default state is Address Bus.
To deactivate the internal pull-up resistor, clear the appropriate
GPIO bit in the GPIOA_PUR register.
Example: GPIOA0, clear bit 0 in the GPIOA_PUR register.
A9
(GPIOA1)
20
A10
(GPIOA2)
21
A11
(GPIOA3)
22
A12
(GPIOA4)
23
A13
(GPIOA5)
24
A14
(GPIOA6)
25
A15
(GPIOA7)
26
Table 2-2 Signal and Package Information for the 160-Pin LQFP
Signal Name
Pin
No.
Type
State
During
Reset
Signal Description
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