參數(shù)資料
型號(hào)： MC56F8255MLD
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 35/88頁(yè)
文件大小： 0K
描述： DSC 64K FLASH 60MHZ 44-LQFP
標(biāo)準(zhǔn)包裝： 160
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 60MHz
連通性： CAN，I²C，LIN，SCI，SPI
外圍設(shè)備： LVD，POR，PWM，WDT
輸入/輸出數(shù)： 35
程序存儲(chǔ)器容量： 64KB（32K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 4K x 16
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 8x12b，D/A 1x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 44-LQFP
包裝： 管件
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
General System Control Information
Freescale Semiconductor
40
Peripheral clocks for Quad Timers and SCIs with a high-speed (2x) option
Power-saving clock gating for peripherals
Controls for enabling/disabling functions of large regulator standby mode with write protection capability
Allowing selected peripherals to run in stop mode to generate stop recovery interrupts
Controls for programmable peripheral and GPIO connections
Software chip reset
I/O short address base location control
Peripheral protection control to provide runaway code protection for safety-critical applications
Controls for output of internal clock sources to CLKO pin
Four general-purpose software control registers that are reset only at power-on
Peripheral stop mode clocking control
5.7
Inter-Module Connections
The operations between on-chip peripherals can be synchronized or cascaded through internal module connections to support
particular applications. Examples include synchronization between ADC sampling and PWM waveform generation for a power
conversion application, and synchronization between timer pulse outputs and DAC waveform generation for a printer
application. The user can program the internal Crossbar Switch or Comparator input multiplexes to connect one on-chip
peripheral’s outputs to other peripherals’ inputs.
5.7.1
Comparator Connections
The MC56F825x/MC56F824x includes three high-speed comparators. Each comparator input has a 4-to-1 input mux, allowing
it to sample a variety of analog sources. Some of these inputs share package pins with the on-chip ADCs; see Table 5
Each comparator is paired with a dedicated, programmable, 5-bit on-chip voltage reference DAC (VREF_DAC). Optionally,
an on-chip 12-bit DAC can be internally fed to each comparator’s positive input 1 (CMPn_P1) or negative input 3 (CMPn_M3).
In addition, all three comparators’ positive input 3 (CMPn_P3) can be connected together to package pin CMP_REF. Other
inputs can be routed to package pins when the corresponding pin is configured for peripheral mode in the GPIO module.
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