參數(shù)資料
型號: MC56F8247VLH
廠商: Freescale Semiconductor
文件頁數(shù): 68/88頁
文件大小: 0K
描述: DSC 48K FLASH 60MHZ 64-LQFP
標準包裝: 160
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 60MHz
連通性: CAN,I²C,LIN,SCI,SPI
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 54
程序存儲器容量: 48KB(24K x 16)
程序存儲器類型: 閃存
RAM 容量: 4K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b,D/A 1x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 64-LQFP
包裝: 管件
MC56F825x/MC56F824x Digital Signal Controller, Rev. 3
Specifications
Freescale Semiconductor
70
2. Parasitic capacitance due to the chip bond pad, ESD protection devices, and signal routing: 2.04 pF
3. 8 pF noise damping capacitor
4. Sampling capacitor at the sample and hold circuit. Capacitor C1 is normally disconnected from the input and is only
connected to it at sampling time: Cgain = 1.4 pF for x1 gain, 2.8 pF for x2 gain, and 5.6 pF for x4 gain.
5. S1 and S2 switch phases are non-overlapping and operate at the ADC clock frequency.
Figure 31. Equivalent Circuit for A/D Loading
7.26 Digital-to-Analog Converter (DAC) Parameters
Table 42. DAC Parameters
Parameter
Conditions/Comments
Symbol
Min
Typ
Max
Unit
DC Specifications
Resolution
12
12
bits
Settling time
At output load
RLD = 3 KΩ
CLD = 400 pf
TBD
2
S
Power-up time
Time from release of PWRDWN
signal until DACOUT signal is
valid
tDAPU
11
S
Accuracy
Integral non-linearity1
Range of input digital words:
410 to 3891 ($19A - $F33)
5% to 95% of full range
INL
+/- 3
+/- 8.0
LSB2
Differential non-linearity1
Range of input digital words:
410 to 3891 ($19A - $F33)
5% to 95% of full range
DNL
+/- 0.8
+/- 1.0
LSB2
Monotonicity
> 6 sigma monotonicity,
< 3.4 ppm non-monotonicity
guaranteed
Offset error1
Range of input digital words:
410 to 3891 ($19A - $F33)
5% to 95% of full range
VOFFSET
+/- 25
+/- 40
mV
Gain error1
Range of input digital words:
410 to 3891 ($19A - $F33)
5% to 95% of full range
EGAIN
+/- .5
+/- 1.5
%
DAC Output
Output voltage range
Within 40 mV of either VREFLX or
VREFHX
VOUT
VREFLX
+0.04V
—VREFHX
- 0.04V
V
AC Specifications
Signal-to-noise ratio
SNR
TBD
dB
Spurious free dynamic
range
SFDR
TBD
dB
Effective number of bits
ENOB
Bits
S1
S2
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