參數(shù)資料
型號(hào): MC56F8036VLF
廠商: Freescale Semiconductor
文件頁數(shù): 52/164頁
文件大小: 0K
描述: IC DGTL SGNL CTLR 16BIT 48-LQFP
標(biāo)準(zhǔn)包裝: 1,250
系列: 56F8xxx
核心處理器: 56800E
芯體尺寸: 16-位
速度: 32MHz
連通性: CAN,I²C,SCI,SPI
外圍設(shè)備: POR,PWM,WDT
輸入/輸出數(shù): 39
程序存儲(chǔ)器容量: 64KB(32K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 4K x 16
電壓 - 電源 (Vcc/Vdd): 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 10x12b; D/A 2x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 48-LQFP
包裝: 托盤
產(chǎn)品目錄頁面: 734 (CN2011-ZH PDF)
Power Consumption
56F8036 Data Sheet, Rev. 6
Freescale Semiconductor
145
10.19 Power Consumption
See Section 10.1 for a list of IDD requirements for the 56F8036. This section provides additional detail
which can be used to optimize power consumption for a given application.
Power consumption is given by the following equation:
A, the internal [static component], is comprised of the DC bias currents for the oscillator, leakage currents,
PLL, and voltage references. These sources operate independently of processor state or operating
frequency.
B, the internal [state-dependent component], reflects the supply current required by certain on-chip
resources only when those resources are in use. These include RAM, Flash memory and the ADCs.
C, the internal [dynamic component], is classic C*V2*F CMOS power dissipation corresponding to the
56800E core and standard cell logic.
D, the external [dynamic component], reflects power dissipated on-chip as a result of capacitive loading
on the external pins of the chip. This is also commonly described as C*V2*F, although simulations on two
of the I/O cell types used on the 56800E reveal that the power-versus-load curve does have a non-zero
Y-intercept.
Power due to capacitive loading on output pins is (first order) a function of the capacitive load and
frequency at which the outputs change. Table 10-23 provides coefficients for calculating power dissipated
in the I/O cells as a function of capacitive load. In these cases:
TotalPower =
Σ((Intercept + Slope*Cload)*frequency/10MHz)
where:
Summation is performed over all output pins with capacitive loads
TotalPower is expressed in mW
Cload is expressed in pF
Total power =
A: internal [static component]
+B: internal [state-dependent component]
+C: internal [dynamic component]
+D: external [dynamic component]
+E: external [static component]
Table 10-23 I/O Loading Coefficients at 10MHz
Intercept
Slope
8mA drive
1.3
0.11mW / pF
4mA drive
1.15mW
0.11mW / pF
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