參數(shù)資料
型號： MC56F8023VLC
廠商： Freescale Semiconductor
文件頁數(shù)： 141/157頁
文件大?。?/td> 0K
描述： IC DSP 16BIT DUAL HARV 32-LQFP
標準包裝： 1,250
系列： 56F8xxx
核心處理器： 56800E
芯體尺寸： 16-位
速度： 32MHz
連通性： I²C，LIN，SCI，SPI
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 26
程序存儲器容量： 32KB（16K x 16）
程序存儲器類型： 閃存
RAM 容量： 2K x 16
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 6x12b; D/A 2x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 32-LQFP
包裝： 托盤
56F8033/56F8023 Data Sheet, Rev. 6
84
Freescale Semiconductor
Figure 6-8 CLKO Select Register (SIM_CLKOUT)
6.3.7.1
Reserved—Bits 15–10
This bit field is reserved. Each bit must be set to 0.
6.3.7.2
PWM3—Bit 9
0 = Peripheral output function of GPIOA[3] is defined to be PWM3
1 = Peripheral output function of GPIOA[3] is defined to be the Relaxation Oscillator Clock
6.3.7.3
PWM2—Bit 8
0 = Peripheral output function of GPIOA[2] is defined to be PWM2
1 = Peripheral output function of GPIOA[2] is defined to be the system clock
6.3.7.4
PWM1—Bit 7
0 = Peripheral output function of GPIOA[1] is defined to be PWM1
1 = Peripheral output function of GPIOA[1] is defined to be 2X system clock
6.3.7.5
PWM0—Bit 6
0 = Peripheral output function of GPIOA[0] is defined to be PWM0
1 = Peripheral output function of GPIOA[0] is defined to be 3X system clock
6.3.7.6
Clockout Disable (CLKDIS)—Bit 5
0 = CLKOUT output function is enabled and will output the signal indicated by CLKOSEL
1 = CLKOUT output function is disabled
6.3.7.7
Clockout Select (CLKOSEL)—Bits 4–0
CLKOSEL selects the clock to be muxed out on the CLKO pin as defined in the following. Internal delay
to CLKO output is unspecified. Signal at the output pad is undefined when CLKO signal frequency
exceeds the rated frequency of the I/O cell. CLKO may not operate as expected when CLKDIS and
CLKOSEL settings are changed.
00000 = Continuous system clock
00001 = Continuous peripheral clock
00010 = 3X system clock
00100.....11111 = Reserved for factory test
6.3.8
Peripheral Clock Rate Register (SIM_PCR)
By default, all peripherals are clocked at the system clock rate, which has a maximum of 32MHz. Selected
Base + $A
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Read
0
PWM3PWM2PWM1PWM0
CLK
DIS
CLKOSEL
Write
RESET
0
1
0
0000
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