External Clock Operation Timing
56F8013/56F8011 Data Sheet, Rev. 12
Freescale Semiconductor
101
10.5 External Clock Operation Timing
Figure 10-4 External Clock Timing
10.6 Phase Locked Loop Timing
Table 10-10 External Clock Operation Timing Requirements1
1. Parameters listed are guaranteed by design.
Characteristic
Symbol
Min
Typ
Max
Unit
Frequency of operation (external clock driver)2
2. See Figure 10-4 for details on using the recommended connection of an external clock driver.
fosc
48
8
MHz
Clock Pulse Width3
3. The high or low pulse width must be no smaller than 6.25ns or the chip may not function.
tPW
6.25
—
ns
External Clock Input Rise Time4
4. External clock input rise time is measured from 10% to 90%.
trise
——
3
ns
External Clock Input Fall Time5
5. External clock input fall time is measured from 90% to 10%.
tfall
——
3
ns
Table 10-11 PLL Timing
Characteristic
Symbol
Min
Typ
Max
Unit
Internal reference relaxation oscillator frequency for
the PLL
frosc
—8—
MHz
PLL output frequency1 (24 x reference frequency)
1. The core system clock will operate at 1/6 of the PLL output frequency.
fop
—192
—
MHz
PLL lock time2
2. This is the time required after the PLL is enabled to ensure reliable operation.
tlock
—
40
100
s
Cycle-to-cycle jitter
tjitterpll
350
ps
External
Clock
VIH
VIL
Note: The midpoint is VIL + (VIH – VIL)/2.
90%
50%
10%
90%
50%
10%
tPW
tfall
trise
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