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參數(shù)資料
| 型號(hào)： | MC54HC541AJ |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Octal 3-State Non-Inverting Buffer/Line Driver/Line Receiver |
| 中文描述： | HC/UH SERIES, 8-BIT DRIVER, TRUE OUTPUT, CDIP20 |
| 封裝： | CERAMIC, DIP-20 |
| 文件頁(yè)數(shù)： | 1/6頁(yè) |
| 文件大?。?/td> | 167K |
| 代理商： | MC54HC541AJ |
SEMICONDUCTOR TECHNICAL DATA
3–1
REV 1
Motorola, Inc. 1995
10/95
"
!"
"
High–Performance Silicon–Gate CMOS
The MC54/74HC541A is identical in pinout to the LS541. The device
inputs are compatible with Standard CMOS outputs. External pullup
resistors make them compatible with LSTTL outputs.
The HC541A is an octal non–inverting buffer/line driver/line receiver
designed to be used with 3–state memory address drivers, clock drivers, and
other bus–oriented systems. This device features inputs and outputs on
opposite sides of the package and two ANDed active–low output enables.
The HC541A is similar in function to the HC540A, which has inverting
outputs.
Output Drive Capability: 15 LSTTL Loads
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 2 to 6V
Low Input Current: 1
μ
A
High Noise Immunity Characteristic of CMOS Devices
In Compliance With the JEDEC Standard No. 7A Requirements
Chip Complexity: 134 FETs or 33.5 Equivalent Gates
18
Y1
2
A1
17
Y2
3
A2
16
Y3
4
A3
15
Y4
5
A4
14
Y5
6
A5
13
Y6
7
A6
12
Y7
8
A7
11
Y8
9
A8
OE1
OE2
1
19
Output
Enables
Data
Inputs
Non–Inverting
Outputs
PIN 20 = VCC
PIN 10 = GND
LOGIC DIAGRAM
Pinout: 20–Lead Packages
(Top View)
19
20
18
17
16
15
14
2
1
3
4
5
6
7
VCC
13
8
12
9
11
10
OE2
Y1
Y2
Y3
Y4
Y5
Y6
Y7
Y8
OE1
A1
A2
A3
A4
A5
A6
A7
A8
GND
L
L
H
X
L
L
X
H
L
H
X
X
FUNCTION TABLE
Inputs
Output Y
OE1
OE2
A
L
H
Z
Z
Z = High Impedance
X = Don’t Care
DW SUFFIX
SOIC PACKAGE
CASE 751D–04
N SUFFIX
PLASTIC PACKAGE
CASE 738–03
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXADW
Ceramic
Plastic
SOIC
J SUFFIX
CERAMIC PACKAGE
CASE 732–03
1
20
1
20
1
20
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