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參數(shù)資料
| 型號(hào)： | MC54HC4353J |
| 廠(chǎng)商： | MOTOROLA INC |
| 元件分類(lèi)： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | Analog Multiplexers/Demultiplexers with Address Latch |
| 中文描述： | TRIPLE 2-CHANNEL, DIFFERENTIAL MULTIPLEXER, CDIP20 |
| 封裝： | CERAMIC, DIP-20 |
| 文件頁(yè)數(shù)： | 5/13頁(yè) |
| 文件大?。?/td> | 477K |
| 代理商： | MC54HC4353J |
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MC54/74HC4351 MC54/74HC4353
High–Speed CMOS Logic Data
DL129 — Rev 6
5
MOTOROLA
Symbol
Parameter
V
25 C
85 C
2.0
Unit
tsu
Minimum Setup Time, Channel–Select to Latch Enable
100
125
125 C
150
ns
(Figure 12)
4.5
0
(Figure 12)
4.5
6.0
16
14
0
24
20
0
6.0
400
400
20
17
400
NOTE:Information on typical parametric values can be found in Chapter 2 of the Motorola High–Speed CMOS Data Book (DL129/D).
Symbol
BW
Parameter
Maximum On–Channel Bandwidth or
(Figure 6)
Test Condition
fin = 1 MHz Sine Wave
V
V
54/74HC
Unit
MHz
Increase fin Frequency Until dB Meter
2.25
– 2.25
51
52
80
95
53
120
(Figure 7)
Adjust fin Voltage to Obtain 0 dBm at VIS
fin = 10 kHz, RL = 600
, CL = 50 pF
2.25
6.00
2.25
– 2.25
– 6.00
– 2.25
– 50
– 50
– 40
Input to Common O/I
(tr = tf = 6 ns)
RL = 600
, CL = 50 pF
4.50
4.50
6.00
– 4.50
– 4.50
– 6.00
105
145
190
(Test does not apply to HC4351)
fin
Sine Wave
2.25
4.50
– 2.25
– 4.50
– 50
– 60
VIS = 4.0 VPP sine wave
* Limits not tested. Determined by design and verified by qualification.
2.25
– 2.25
0.10
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