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參數(shù)資料
| 型號： | MC44871DTB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | PLL TUNING CIRCUIT WITH HIGH SPEED I2C BUS AND 30 V TUNING SUPPLY |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO16 |
| 封裝： | PLASTIC, TSSOP-16 |
| 文件頁數(shù)： | 6/12頁 |
| 文件大小： | 198K |
| 代理商： | MC44871DTB |
MC44871
6
MOTOROLA ANALOG IC DEVICE DATA
HIGH SPEED I2C BUS
(The circuit is controlled by a I2C bus with a Serial Data [SDA], Serial Clock [SCL], Chip Address
Control [ADD] inputs. The device I2C bus has a read mode [odd addresses] and a write mode [even addresses].
ELECTRICAL CHARACTERISTICS
(VCC = 5.0 V, TA = 25
°
C, unless otherwise specified.)
Characteristic
Pin
Symbol
Min
Typ
Max
Unit
Type
SDA/SCL Output Current at 0 V
13, 14
–
–
10
μ
A
A
SDA/SCL Low Input Level
13, 14
VIL
VIH
–
–
1.5
V
B
SDA/SCL High Input Level
13, 14
3.0
–
–
V
B
SDA/SCL Input Current for Input Level from 0.4 V to 0.3 VCC
SDA/SCL Input Level
13, 14
–5.0
0
5.0
μ
A
C
13, 14
0
–
VCC +
0.3
V
D
ADD Input Level
12
–0.01
VCC
–
1.1 VCC
D
SDA/SCL Capacitance
13, 14
Ci
–
–
10
pF
C
SDA Low Output Level (sinking 3.0 mA)
13
–
0.3
1.0
V
A
SDA Low Output Level (sinking 15 mA)
13
–
–
1.5
V
C
TIMING CHARACTERISTICS
Characteristic
Pin
Symbol
Min
Typ
Max
Unit
Type
Bus Clock Frequency
14
0
–
800
kHz
C
Bus Free Time Between Stop and Start
–
Tbuf
Tsu;sta
Thd;sta
Tsu;dat
Thd;dat
Tsu;sto
Thd;sto
Tack;low
200
–
–
ns
C
Setup Time for Start Conditions
–
500
–
–
ns
C
Hold Time for Start Condition
–
500
–
–
ns
C
Data Setup Time
–
0
–
–
ns
C
Data Hold Time
–
0
–
–
ns
C
Setup Time for Stop Condition
–
500
–
–
ns
C
Hold time for Stop Condition
–
500
–
–
ns
C
Acknowledge Propagation Delay
–
–
300
ns
C
SDA Fall Time at 3.0 mA sink I and 130 pF Load
13
–
–
50
ns
C
SDA Fall Time at 3.0 mA sink I and 400 pF Load
13
–
–
80
ns
C
SDA/SCL Rise Time
13, 14
–
–
300
ns
C
SCL Fall Time
13, 14
–
–
300
ns
C
Pulse Width of Spikes Suppressed by the Input Filter
13,14
Tsp
–
–
50
ns
C
0 V
VCC
VIH
VIL
Not Defined
Tbuf
Thd;dat
Tsu;dat
Tsu;stoThd;sta
Tack:low
Start
Stop
Tsu;sta
Chip address
Thd;sto
Start
Stop
SDA
SCL
SDA
SCL
SDA
SCL
ACK
Timings Definition
Levels Definition
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