
MC44724/5 Rev 0.21 03/25/97
No.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
7
CSYNC
CSYNC
525
524
1
2
3
4
5
6
7
8
9
10
11
21
22
23
262
261
263
264
265
266
267
268
269
270
271
272
273
283
284
285
Fig 5 : Sync Timing::525/60 Interlaced System in Master Mode
Vsync
Hsync
Vsync
Hsync
sub-address71[7] =0
Fsync
Fsync polarity
sub-address71[3]
Vsync polarity
sub-address71[4]
Fsync
Fig 4 : Digital Input Timing(625/50 system) in Master Mode
70(hex){[1:0]=01}
1440T
Hsync phase
sub-address71[2:0]
+4T delay
Hsync
clock
128T
T
264T
Hsync polarity
sub-address71[5]
-3T delay
DVIN0~7
Cr
718
Cb
718
Y
718
Y
719
00
00
FF
Cb
2
Cr
0
Cb
0
Y
0
Y
1
Y
2
INVALID
00
00
XY
FF
Y
718
Y
719
TP1~8
Cr
718
Cb
718
Cb
2
Cr
0
Cb
0
INVALID
DVIN0~7
Y2
Y
1
Y
0
INVALID
16-bit input mode
8-bit input mode
Cb
718
Cr
718
Cr
2
Cr
0
Cb
0
or