參數(shù)資料
型號(hào)： MC34920
廠商： 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述： 2.8 Ohm(Typ) Quad H-Bridge Motor Driver(2.8歐（典型值）四H橋電機(jī)驅(qū)動(dòng)器)
中文描述： 2.8歐姆（典型值）四H橋電機(jī)驅(qū)動(dòng)器（2.8歐（典型值）四魔橋電機(jī)驅(qū)動(dòng)器）
文件頁(yè)數(shù)： 14/28頁(yè)
文件大小： 813K
代理商： MC34920
34920
14
Go to: www.freescale.com
SYSTEM/APPLICATION INFORMATION
INTRODUCTION
Introduction
The 34920 is a multifunctional analog IC that can be used in
printer and scanner applications. It integrates two switching
voltage regulator circuits, four H-bridge drivers, and a reset
circuit in a single IC. All 34920 control lines are compatible with
CMOS type 3.3 V and 5.0 V logic.
Switching Voltage Regulator Circuits
Two switching voltage regulators provide the following
voltages from an unregulated input of 21 V to 42 V DC. Both are
buck-type switching regulators using a MOSFET (internal to the
34920), current sense resistor (internal to the 34920), Schottky
diode (external to the 34920), external inductor, and filter
capacitor.
V1 Voltage Regulator – This regulator is programmable,
has a duty cycle of 37%, and provides either 3.3 V (+5%/
-4%) or 5.0 V (+5%/-4%) at a current of 10 mA (minimum)
to 500 mA (maximum).
V2 Voltage Regulator – This regulator has a
programmable output voltage (by means of an external
resistor divider network) in the range of 10 V to 15 V ±2%
with a VB+ supply voltage range of 21 V to 42 V.
The V2 voltage regulator is controlled by an Enable bit in the
serial register that allows software to turn this regulator on and
off. However, the Enable bit does not effect the V1 voltage
regulator. The Enable bit will disable the V2 voltage regulator
and disable all motor driver circuits.
Motor Drivers
The two motor drivers can be selectable as either a bi-
directional DC motor driver, with PWM control and peak
currents of 2.4 A, or a bipolar step motor driver, with average
current levels of 183 mA and 550 mA per phase, and quarter
step mode capability. In step mode, both drivers are capable of
being operated in the quarter step mode.
RESET
Generation
The 34920 provides an output,
RESET
, that drives an
external reset signal to the system microprocessor and/or the
system digital logic IC. This signal is an active low logic level
signal that is derived by monitoring the level of the VB+ and
V1_FB terminals.
When
RESET
is asserted, either internally or from an
external source, all 34920 motor driver outputs will be in their
inactive states, and the serial input port will be loaded with the
reset value.
FUNCTIONAL DESCRIPTION
Input Power Supply (V
VB+
)
The input voltage for the switching regulators and motor
drivers. V
VB+
is a voltage range of 21 V to 42 V.
CMOS Logic Level
CMOS logic level specifications are described on
page 6
of
the Static Electrical Characteristics table.
34920 Input
Table 3
, page 15, describes the 34920 input specifications.
Serial Input Port
The 34920 provides a serial input port for bit depth of 13 bits
of input. This port provides an interface between the 34920 and
the digital controller IC. This port is write-only. The interface
consists of three signal lines: chip select (
CS
, active low), serial
clock (SCLK), and serial data input (SDI).
The digital controller initiates a serial transfer by pulling low
the chip select line (
CS
). It then generates 13 clock pulses on
the SCLK terminal while presenting the serial data on the serial
data input (SDI). The 34920 presents the data on SDI one setup
time (t
DSU
) before the rising edge of SCLK. The data is held
constant for the data hold time (t
DHD
) beyond the SCLK rising
edge. The data is shifted into the 34920 on the rising edge of
SCLK. The least significant bit (LSB) is the first to be shifted out
of the 34920 on the rising edge of SCLK, followed by the
remaining bits to the last of the 13 bits, which is the most
significant bit (MSB). The
CS
line is then returned to a high
state. The low-to-high transition of
CS
will load the data into the
internal 34920 input register, where all the inputs are presented
to their appropriate functions in a parallel fashion.
Note
The minimum off-time (
CS
signal equal to logic [1]) for
the
CS
signal needs to be at least 1.0 t
DSU
delay + 1.0 t
DHD
delay. This will provide the time for the 34920 to clear the serial
input data register (transfer the serial data in parallel to internal
latches that use the data) and thereby avoid a data overrun
condition and loss of data. See the serial input port timing data
in the Dynamic Electrical Characteristics table,
page 10
.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
n
.
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