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| 型號： | MC34250FTA |
| 廠商： | MOTOROLA INC |
| 元件分類： | 光電元器件 |
| 英文描述： | HARD DISK DRIVE READ CHANNEL |
| 中文描述： | READ CHANNEL, PQFP64 |
| 封裝： | 10 X 10 MM, PLASTIC, TQFP-64 |
| 文件頁數(shù)： | 1/4頁 |
| 文件大?。?/td> | 141K |
| 代理商： | MC34250FTA |
Device
Operating
Temperature Range
Package
SEMICONDUCTOR
TECHNICAL DATA
HARD DISK DRIVE
READ CHANNEL
ORDERING INFORMATION
MC34250FTA
TA = 0
°
to +70
°
C
TQFP–64
FTA SUFFIX
PLASTIC PACKAGE
CASE 840F
(Thin QFP)
Order this document from Analog Marketing
64
1
right to change or discontinue this product without notice.
!
The Motorola MC34250 is a fully integrated partial response maximum
likelihood disk drive read/write channel for use in zoned recording
applications. This device integrates the AGC, active filter, 7 tap equalizer,
Viterbi detector, frequency synthesizer, servo demodulator, 8/9 rate (0,4/4)
Encoder/Decoder with write precompensation and power management in a
single 64 pin 10 mm x 10 mm TQFP package.
FEATURES:
50 to 200 MBPS Programmable Data Rate
800 mW at 200 MBPS and 5.0 V
Channel Monitor Output
Programmable AGC Charge Pump Currents with Different Values for
Data and Servo Envelope Modes and Gain Gradient Mode
Programmable AGC Peak Detector Droop Currents with Different
Values for Data and Servo Envelope Modes
Separate AGC Charge Pump Outputs for Data and Servo Modes
Programmable Dual Threshold Qualifier or Hysteresis Comparator Type
Pulse Detector for Servo Data Detection.
ERD and Polarity Outputs for Servo Timing and Raw Encoded Data
Integrated 7 pole 0.05
°
Equiripple Linear Phase Filter with
Programmable Bandwidth from 5.0 MHz to 80 MHz and Different Values
for Both Data and Servo Modes
Programmable Symmetrical Boost from 0 to 10 dB and Different Values
for Data and Servo Modes
Programmable Asymmetrical Boost of Up to
±
40% of Nominal Filter
Group Delay in Both Data and Servo Modes
7 Tap Continuous Time Transversal Equalizer with 8 Bit Programmable
Tap Weights and Integrated Decision Directed Sign–Sign Least Mean
Squared Adaptation
Internal Offset Cancellation Loops
Fast Acquisition Data Phase Locked Loop with Zero Phase Restart
Programmable Data Phase Locked Loop Charge Pump Current
Integrated Soft Decision Viterbi Detectors with Programmable Merge
References
Integrated 8/9 Rate (0,4/4) Encoder and Decoder with Code Scrambler
and Descrambler
Programmable 2/4/8 Bit NRZ Data Interface
Programmable Write Precompensation Delays Locked to the Frequency
Synthesizer
Differential PECL Write Data Outputs
External Write Data Path for DC Erase or Other Non–Encoded Data
Integrated Write Current DAC
Programmable Power Management
Bi–Directional Serial Microprocessor Interface
Various Test Modes Controlled Via the Serial Microprocessor Interface
This document contains information on a product under development. Motorola reserves the
Motorola, Inc. 1996
Issue 0
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