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參數(shù)資料
| 型號： | MC34072VPG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 3/26頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC OPAMP DUAL SGL SUPP HS 8DIP |
| 標準包裝： | 50 |
| 放大器類型： | 通用 |
| 電路數(shù)： | 2 |
| 轉(zhuǎn)換速率： | 13 V/µs |
| 增益帶寬積： | 4.5MHz |
| 電流 - 輸入偏壓： | 100nA |
| 電壓 - 輸入偏移： | 1000µV |
| 電流 - 電源： | 1.9mA |
| 電流 - 輸出 / 通道： | 30mA |
| 電壓 - 電源，單路/雙路(±)： | 3 V ~ 44 V，±1.5 V ~ 22 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 8-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 8-PDIP |
| 包裝： | 管件 |
| 其它名稱： | MC34072VPGOS |
MC34071,2,4,A MC33071,2,4,A, NCV33072,4,A
http://onsemi.com
11
Figure 34. Supply Current versus
Supply Voltage
Figure 35. Power Supply Rejection
versus Temperature
Figure 36. Channel Separation versus Frequency
Figure 37. Input Noise versus Frequency
VCC, |VEE|, SUPPLY VOLTAGE (V)
CCI
,SUPPL
Y
CURRENT
(mA)
0
5.0
10
15
20
25
TA = 25°C
TA = 125°C
TA = -55°C
TA, AMBIENT TEMPERATURE (°C)
PSR,
POWER
SUPPL
Y
REJECTION
(dB)
-55
-25
0
25
50
75
100
125
VCC = +15 V
VEE = -15 V
(
DVCC = +1.5 V)
(
DVEE = +1.5 V)
+PSR
-PSR
f, FREQUENCY (kHz)
CHANNEL
SEP
ARA
TION
(dB)
10
20
30
50
70
100
200
300
VCC = +15 V
VEE = -15 V
TA = 25°C
f, FREQUENCY (kHz)
n
e,
INPUT
NOICE
VOL
TAGE
(
i,
INPUT
NOISE
CURRENT
(pA
)
10
100
1.0 k
10 k
100 k
nV
Hz)
√
Hz
√
n
Voltage
Current
9.0
8.0
7.0
6.0
5.0
4.0
105
95
85
75
65
120
100
80
60
40
20
0
70
60
50
40
30
20
10
0
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0
DVO
ADM
+
-
DVCC
DVEE
DVO/ADM
DVCC
+PSR = 20 Log
DVO/ADM
DVEE
-PSR = 20 Log
VCC = +15 V
VEE = -15 V
VCM = 0
TA = 25°C
Quad device
APPLICATIONS INFORMATION
CIRCUIT DESCRIPTION/PERFORMANCE FEATURES
Although the bandwidth, slew rate, and settling time of the
MC34071 amplifier series are similar to op amp products
utilizing JFET input devices, these amplifiers offer other
additional distinct advantages as a result of the PNP
transistor differential input stage and an all NPN transistor
output stage.
Since the input common mode voltage range of this input
stage includes the VEE potential, single supply operation is
feasible to as low as 3.0 V with the common mode input
voltage at ground potential.
The input stage also allows differential input voltages up
to
±44 V, provided the maximum input voltage range is not
exceeded. Specifically, the input voltages must range
between VEE and VCC supply voltages as shown by the
maximum
rating
table.
In
practice,
although
not
recommended, the input voltages can exceed the VCC
voltage by approximately 3.0 V and decrease below the VEE
voltage by 0.3 V without causing product damage, although
output phase reversal may occur. It is also possible to source
up to approximately 5.0 mA of current from VEE through
either inputs clamping diode without damage or latching,
although phase reversal may again occur.
If one or both inputs exceed the upper common mode
voltage limit, the amplifier output is readily predictable and
may be in a low or high state depending on the existing input
bias conditions.
Since the input capacitance associated with the small
geometry input device is substantially lower (2.5 pF) than
the typical JFET input gate capacitance (5.0 pF), better
frequency response for a given input source resistance can
be achieved using the MC34071 series of amplifiers. This
performance feature becomes evident, for example, in fast
settling DtoA current to voltage conversion applications
where the feedback resistance can form an input pole with
the input capacitance of the op amp. This input pole creates
a 2nd order system with the single pole op amp and is
therefore detrimental to its settling time. In this context,
lower input capacitance is desirable especially for higher
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