參數資料
| 型號： | MC33897EF |
| 廠商： | Freescale Semiconductor |
| 文件頁數： | 2/19頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANSCEIVER CAN SW 14-SOIC |
| 標準包裝： | 55 |
| 類型： | 收發(fā)器 |
| 驅動器/接收器數： | 1/1 |
| 規(guī)程： | CAN |
| 電源電壓： | 12V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 14-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 14-SOICN |
| 包裝： | 管件 |
Analog Integrated Circuit Device Data
10
Freescale Semiconductor
33897
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
BUS (CONTINUED)
High Voltage Rising Output Delay
200
Ω ≤ R
L ≤ 3332 Ω, 1.0 μs ≤ Load Time Constants ≤ 4.0 μs
Measured from TXD=VIL to VBUS as follows:
Max Time to VBUSMOD = 3.7 V, 6.0 V ≤ VBATT ≤ 26.5 V
Min Time to VBUSMOD = 1.0 V, 6.0 V ≤ VBATT ≤ 26.5 V
Max Time to VBUSMOD = 9.4 V, 12.0 V ≤ VBATT ≤ 26.5 V
tDLYHVRO
2.0
–
6.3
18
μs
High Voltage Falling Output Delay
200
Ω ≤ R
L ≤ 3332 Ω, 1.0 μs ≤ Load Time Constants ≤ 4.0 μs,
12.0 V
≤ V
BATT ≤ 26.5 V
Measured from TXD=VIH to VBUS as follows:
Max Time to VBUSMOD = 1.0 V
Min Time to VBUSMOD = 3.7 V
tDLYHVFO
1.8
–
14
μs
RECEIVER RXD
Receive Delay Time (5.0 V
≤ V
BATT ≤ 26.5 V)
Awake
t RDLY
0.2
–
1.0
μs
Receive Delay Time (BUS Rising to RXD Falling, 5.0 V
≤ V
BATT ≤ 26.5 V)
Sleep
t RDLYSL
10
–
70
μs
CNTL
CNTL Falling Delay Time (5.0 V
≤ V
BATT ≤ 26.5 V)
tCNTLFDLY
300
–
1000
ms
Notes
12.
Table 5. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions of -40
°C ≤ T
A ≤ 125 °C, unless otherwise stated. Voltages are relative to GND unless
otherwise noted. All positive currents are into the pin. All negative currents are out of the pin.
Characteristic
Symbol
Min
Typ
Max
Unit
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