參數(shù)資料
型號(hào)： MC33689DWBR2
廠商： Freescale Semiconductor
文件頁數(shù)： 5/31頁
文件大小： 0K
描述： IC SYSTEM BASE W/LIN 32-SOIC
標(biāo)準(zhǔn)包裝： 1,000
應(yīng)用： 自動(dòng)鏡像控制
接口： SPI
電源電壓： 5.5 V ~ 18 V
封裝/外殼： 32-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 32-SOIC
包裝： 帶卷 (TR)
安裝類型： 表面貼裝
配用： KIT33689DWBEVB-ND - KIT FOR 33689 SBC WITH LIN
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
33689
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
CURRENT SENSE OPERATIONAL AMPLIFIER
Supply Voltage Rejection Ratio (16)
SVR
60
—
dB
Common Mode Rejection Ratio (16)
CMR
70
—
dB
Gain Bandwidth (16)
GBP
1.0
—
MHz
Output Slew Rate
SR
0.5
—
V/
μs
Phase Margin
PHMO
40
—
deg.
Open Loop Gain (16)
OLG
—
85
—
dB
L1 AND L2 INPUT PINS
Wake-Up Filter Time (16)
tWUF
8.0
20
38
μs
STATE MACHINE TIMING
Delay Between CS LOW-to-HIGH Transition (at End of SPI Stop Command)
and Stop Mode Activation (16)
Minimum Watchdog Period
No Watchdog Selected
Maximum Watchdog Period
tSTOP
1.4
6.0
12
—
5.0
30
50
μs
Interrupt Low-Level Duration
tINT
7.0
10
13
μs
Internal Oscillator Frequency Accuracy (All Modes, for Information Only)
fOSC
-35
—
35
%
Normal Request Mode Time-Out (Normal Request Mode)
tNRTOUT
97
150
205
ms
Delay Between SPI Command and HS1 or HS2 Turn On (17)
Normal Mode, VSUP > 9.0 V, VHS ≥ 0.2 VVS2
tSHSON
—
20
μs
Delay Between SPI Command and HS1 or HS2 Turn Off (17)
Normal Mode, VSUP > 9.0 V, VHS ≤ 0.8 VVS2
tSHSOFF
—
20
μs
Delay Between SPI Command and HS3 Turn On (17)
Normal Mode, VSUP > 9.0 V, VHS ≥ 0.2 VVS2
tSHSON
—
20
μs
Delay Between SPI Command and HS3 Turn Off (17)
Normal Mode, VSUP > 9.0 V, VHS ≤ 0.8 VVS2
tSHSOFF
—
20
μs
Delay Between Normal Request and Normal Mode After a Watchdog Trigger
Command (Normal Request Mode) (16)
tSNR2N
7.0
15
30
μs
Delay Between CS Wake-Up (CS LOW to HIGH) in Stop Mode and:
Normal Request Mode, VDD ON and RST HIGH
First Accepted SPI Command
tWUCS
tWUSPI
15
90
40
—
80
N/A
μs
Delay Between Interrupt Pulse in Stop Mode After Wake-Up and First
Accepted SPI Command
tS1STSPI
30
—
N/A
μs
Minimum Time Between Rising and Falling Edge on the CS
t2CS
15
—
μs
Notes
16.
Parameter guaranteed by design; however, it is not production tested.
17.
When IN input is set to HIGH, delay starts at falling edge of clock cycle #8 of the SPI command and start of device activation/deactivation.
30 mA load on high-side switches. Excluding rise or fall time due to external load.
18.
When IN is used to control the high-side switches, delays are measured between IN and HS1 or HS2 ON /OFF. 30 mA load on high-side
switches, excluding rise or fall time due to external load.
19.
Delay between turn on or turn off command and HS ON or HS OFF, excluding rise or fall time due to external load.
Table 4. Dynamic Electrical Characteristics (continued)
Characteristics noted under conditions 5.5 V
≤ V
SUP ≤ 18 V, - 40°C ≤ T
A ≤ 125°C, GND = 0.0 V unless otherwise noted.
Typical values noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
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