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參數(shù)資料
| 型號： | MC33567D-1G |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 6/12頁 |
| 文件大小： | 88K |
| 描述： | IC REG CTRLR DUAL OUT 8-SOIC |
| 產(chǎn)品變化通告： | Product Obsolescence 13/Apr/2009 |
| 標(biāo)準(zhǔn)包裝： | 98 |
| 類型： | 正，固定式 |
| 輸出數(shù)： | 2 |
| 輸出電壓： | 1.52V，1.82V |
| 電流 - 電源： | 6.3mA |
| 輸入電壓： | 9 V ~ 12.5 V |
| 工作溫度： | 0°C ~ 80°C |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOICN |
| 包裝： | 管件 |
MC33567
http://onsemi.com
6
The output capacitor capacitance and ESR required for
using the MTD3055VL as external driver are calculated as
follows:
w
f
+
1
C
i
?R
+
1
(1240 pF ) 600 pF) ?(50 W)
+ 10.87 MHz
w
p
+
1
w
1
)
1
w
f
* 1
+
1
5 MHz
)
1
10.87 MHz
* 1
+ 3.42 MHz
1
20 ?/DIV>
1 )
w
a
(3 ?w
p
)
?/DIV>
1
g
m
v R
s
v
(3 ?w
p
)
w
a
?/DIV>
1
g
m
1
20 ?/DIV>
1 )
5 MHz
(3 ?3.42 MHz)
?/DIV>
1
8.8 mhos
v R
s
v
(3 ?3.42 MHz)
5 MHz
?/DIV>
1
8.8 mhos
3.8 mW v R
s
v 233.2 mW
selecting an ESR of 30 mW, we have:
C
o
w
5
R
s
?/DIV>
1
w
a
)
1
w
p
C
o
w
5
30 mW
?/DIV>
1
5 MHz
)
1
3.42 MHz
C
o
w 82.07 mF
100 礔 is selected as it is an industry standard value.
Please note that if the system is designed to work with
several drivers, the system has to be designed around the
driver with higher gain to insure stability for all of them.
The design guidelines discussed in this section are
conservative enough that satisfactory results may be
obtained with devices that lie just outside of these
guidelines, although deviation from these guidelines will
generally cause instability. For a more detailed analysis on
linear regulators stability please refer to ON Semiconductor
application note AND8037/D.
Adjustable Output Voltage:
The MC33567 will regulate V
out
to its preset voltage level,
referenced at the sense pin. However, other V
out
levels can
be obtained scaling the sense voltage. This is done using a
resistive network between the load and the sense pin as
shown in Figure 6.
Figure 6. Output Voltage Scaling Using
Resistive Network
SENSE
V
in
R2
DRV
R
INT
+
V
out(new)
+
V
out
R1
I
SENSE
1.8 kW
The regulator will increase the load voltage until the
SENSE pin voltage reaches the regulator voltage level, V
out
.
The new output voltage, V
out(new)
, is calculated as follows:
V
out(new)
+ V
out
) R
1
*
V
out
R
2
) I
SENSE
Please note that in this configuration R
2
and the sense
internal resistor are in parallel. The parallel combination
will reduce the effective resistance of R
2
. If R
2
is in the range
of R
INT
, the parallel combination will be almost half of the
original intended value of R
2
. This will cause V
out(new)
to be
smaller than calculated using the above equation. This is
avoided making R
2
as small as possible, probably in the
range of 10 to 50 Ohms. V
out(new)
is limited by the external
driver drain current and its required GateSource voltage as
well as the Drive Output Voltage, V
drv
.
PCB Layout Guidelines
It is recommended that the MC33567 be placed as
physically close as possible to the external series pass
MOSFET transistors. Use short traces to minimize
extraneous signals from being induced on the SENSE or
DRV line. Also, avoid routing the SENSE line near the load
and input current path, as well as the GND return current
path to prevent signal coupling.
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