
MC33340
6
MOTOROLA ANALOG IC DEVICE DATA
OPERATING DESCRIPTION
The MC33340 starts up in the fast charge mode when
power is applied to VCC. A change to the trickle mode can
occur as a result of three possible conditions. The first is if the
Vsen input voltage is above 2.0 V or below 1.0 V. Above 2.0 V
indicates that the battery pack is open or disconnected, while
below 1.0 V indicates the possibility of a shorted or defective
cell. The second condition is if a negative slope in battery
voltage is detected after a minimum of 177 seconds of fast
charging. This indicates that the battery pack is fully charged.
The third condition is either due to the battery pack being out
of a programmed temperature range, or that the preset timer
period has been exceeded.
There are three conditions that will cause the controller to
return from trickle to fast charge mode. The first is if the Vsen
input voltage moved to within the 1.0 to 2.0 V range from
initially being either too high or too low. The second is if the
battery pack temperature moved to within the programmed
temperature range, but only from initially being too cold. Third
is by cycling VCC off and then back on causing the internal
logic to reset. A concise description of the major circuit blocks
is given below.
Negative Slope Voltage Detection
A representative block diagram of the negative slope
voltage detector is shown in Figure 9. It includes a
Synchronous Voltage to Frequency Converter, a Sample
Timer, and a Ratchet Counter. The Vsen pin is the input for the
Voltage to Frequency Converter (VFC), and it connects to the
rechargeable battery pack terminals through a resistive
voltage divider. The input has an impedance of
approximately 6.0 M
and a maximum voltage range of
–1.0 V to VCC + 0.6 V or 0 V to 10 V, whichever is lower. The
10 V upper limit is set by an internal zener clamp that
provides protection in the event of an electrostatic discharge.
The VFC is a charge–balanced synchronous type which
generates output pulses at a rate of FV = Vsen (24 kHz).
The Sample Timer circuit provides a 95 kHz system clock
signal (SCK) to the VFC. This signal synchronizes the FV
output to the other Sample Timer outputs used within the
detector. At 1.38 second intervals the Vsen Gate output goes
low for a 33 ms period. This output is used to momentarily
interrupt the external charging power source so that a precise
voltage measurement can be taken. As the Vsen Gate goes
low, the internal Preset control line is driven high for 11 ms.
During this time, the battery voltage at the Vsen input is
allowed to stabilize and the previous FV count is preloaded.
At the Preset high–to–low transition, the Convert line goes
high for 22 ms. This gates the FV pulses into the ratchet
counter for a comparison to the preloaded count. Since the
Convert time is derived from the same clock that controls the
VFC, the number of FV pulses is independent of the clock
frequency. If the new sample has more counts than were
preloaded, it becomes the new peak count and the cycle is
repeated 1.38 seconds later. If the new sample has two fewer
counts, a less than peak voltage event has occurred, and a
register is initialized. If two successive less than peak voltage
events occur, the –
V ‘AND’ gate output goes high and the
Fast/Trickle output is latched in a low state, signifying that the
battery pack has reached full charge status. Negative slope
voltage detection can only occur after 177 seconds have
elapsed in the fast charge mode. The trickle mode holdoff
time is implemented to ignore any initial drop in voltage that
may occur when charging batteries that have been stored for
an extended time period. The negative slope voltage detector
has a maximum resolution of 2.0 V divided by 1023, or 1.955
mV per count with an uncertainty of
±
1.0 count. This yields a
detection range of 1.955 mV to 5.865 mV. In order to obtain
maximum sensing accuracy, the R2/R1 voltage divider must
be adjusted so that the Vsen input voltage is slightly less than
2.0 V when the battery pack is fully charged. Voltage
variations due to temperature and cell manufacturing must
be considered.
Figure 9. Negative Slope Voltage Detector
Vsen
Input
Synchronous
Voltage to
Frequency
Converter
FV = Vsen (24 kHz)
Ck
C
P
Trickle Mode
Holdoff 160s
Over Under
Temperature
Charge
Timer
F/T
UVLO
High
Low
Battery Detect
Logic
–
V
SCK
95 kHz
Vsen Gate
Vsen Gate
Preset
Convert
11 ms
1.38 s
22 ms
Rachet Counter Convert
0 to 1023 FV Pulses
Rachet
Counter
Sample
Timer