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型號：	MC312XDP512J1MPVR
廠商：	FREESCALE SEMICONDUCTOR INC
元件分類：	微控制器/微處理器
英文描述：	16-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP112
封裝：	20 X 20 MM, QFP-112.
文件頁數(shù)：	869/1350頁
文件大?。?/td>	7418K
代理商：	MC312XDP512J1MPVR

Chapter 14 Voltage Regulator (S12VREG3V3V5)

MC9S12XDP512 Data Sheet, Rev. 2.17

Freescale Semiconductor

14.4.2.2

Reduced Power Mode

In reduced power mode, the gate of the output transistor is connected directly to a reference voltage to

reduce power consumption.

Low-Voltage Detect (LVD)

Subblock LVD is responsible for generating the low-voltage interrupt (LVI). LVD monitors the input

voltage (VDDA–VSSA) and continuously updates the status ag LVDS. Interrupt ag LVIF is set whenever

status ag LVDS changes its value. The LVD is available in FPM and is inactive in reduced power mode

or shutdown mode.

Power-On Reset (POR)

This functional block monitors VDD. If VDD is below VPORD, POR is asserted; if VDD exceeds VPORD,

the POR is deasserted. POR asserted forces the MCU into Reset. POR Deasserted will trigger the power-on

Low-Voltage Reset (LVR)

Block LVR monitors the primary output voltage VDD. If it drops below the assertion level (VLVRA) signal,

LVR asserts; if VDD rises above the deassertion level (VLVRD) signal, LVR deasserts. The LVR function

is available only in full peformance mode.

Regulator Control (CTRL)

This part contains the register block of VREG_3V3 and further digital functionality needed to control the

operating modes. CTRL also represents the interface to the digital core logic.

Autonomous Periodical Interrupt (API)

Subblock API can generate periodical interrupts independent of the clock source of the MCU. To enable

the timer, the bit APIFE needs to be set.

The API timer is either clocked by a trimmable internal RC oscillator or the bus clock. Timer operation

will freeze when MCU clock source is selected and bus clock is turned off. See CRG specication for

details. The clock source can be selected with bit APICLK. APICLK can only be written when APIFE is

The APIR[11:0] bits determine the interrupt period. APIR[11:0] can only be written when APIFE is

cleared. As soon as APIFE is set, the timer starts running for the period selected by APIR[11:0] bits. When

the congured time has elapsed, the ag APIF is set. An interrupt, indicated by ag APIF = 1, is triggered

if interrupt enable bit APIE = 1. The timer is started automatically again after it has set APIF.

The procedure to change APICLK or APIR[11:0] is rst to clear APIFE, then write to APICLK or

APIR[11:0], and afterwards set APIFE.

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相關(guān)代理商/技術(shù)參數(shù)	參數(shù)描述
MC312XDP512J1VAAR	制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCS12X Microcontrollers
MC312XDP512J1VFUR	制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCS12X Microcontrollers
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MC312XDP512J1VPVR	制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:HCS12X Microcontrollers
MC3130F	制造商:Rochester Electronics LLC 功能描述:- Bulk

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