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參數(shù)資料
| 型號(hào)： | MC14XXXBDW |
| 廠商： | Motorola, Inc. |
| 英文描述： | BCD-TO-SEVEN SEGMENT LATCH/DECODER/DRIVER |
| 中文描述： | BCD碼到七段鎖存器/解碼器/驅(qū)動(dòng)器 |
| 文件頁數(shù)： | 3/9頁 |
| 文件大?。?/td> | 135K |
| 代理商： | MC14XXXBDW |
MOTOROLA CMOS LOGIC DATA
363
MC14511B
Characteristic
Symbol
Vdc
Min
Typ
Max
Unit
Output Rise Time
tTLH = (0.40 ns/pF) CL + 20 ns
tTLH = (0.25 ns/pF) CL + 17.5 ns
tTLH = (0.20 ns/pF) CL + 15 ns
Output Fall Time
tTHL = (1.5 ns/pF) CL + 50 ns
tTHL = (0.75 ns/pF) CL + 37.5 ns
tTHL = (0.55 ns/pF) CL + 37.5 ns
Data Propagation Delay Time
tPLH = (0.40 ns/pF) CL + 620 ns
tPLH = (0.25 ns/pF) CL + 237.5 ns
tPLH = (0.20 ns/pF) CL + 165 ns
tTLH
5.0
10
15
—
—
—
40
30
25
80
60
50
ns
tTHL
5.0
10
15
—
—
—
125
75
65
250
150
130
ns
tPLH
5.0
10
15
—
—
—
640
250
175
1280
500
350
ns
tPHL = (1.3 ns/pF) CL + 655 ns
tPHL = (0.60 ns/pF) CL + 260 ns
tPHL = (0.35 ns/pF) CL + 182.5 ns
tPHL
5.0
10
15
—
—
—
720
290
200
1440
580
400
Blank Propagation Delay Time
tPLH = (0.30 ns/pF) CL + 585 ns
tPLH = (0.25 ns/pF) CL + 187.5 ns
tPLH = (0.15 ns/pF) CL + 142.5 ns
tPLH
5.0
I0
15
—
—
—
600
200
150
750
300
220
ns
tPHL = (0.85 ns/pF) CL + 442.5 ns
tPHL = (0.45 ns/pF) CL + 177.5 ns
tPHL = (0.35 ns/pF) CL + 142.5 ns
tPHL
5.0
10
15
—
—
—
485
200
160
970
400
320
Lamp Test Propagation Delay Time
tPLH = (0.45 ns/pF) CL + 290.5 ns
tPLH = (0.25 ns/pF) CL + 112.5 ns
tPLH = (0.20 ns/pF) CL + 80 ns
tPLH
5.0
10
15
—
—
—
313
125
90
625
250
180
ns
tPHL = (1.3 ns/pF) CL + 248 ns
tPHL = (0.45 ns/pF) CL + 102.5 ns
tPHL = (0.35 ns/pF) CL + 72.5 ns
tPHL
5.0
10
15
—
—
—
313
125
90
625
250
180
Setup Time
tsu
5.0
10
15
100
40
30
—
—
—
—
—
—
ns
Hold Time
th
5.0
10
15
60
40
30
—
—
—
—
—
—
ns
Latch Enable Pulse Width
tWL
5.0
10
15
520
220
130
260
110
65
—
—
—
ns
* The formulas given are for the typical characteristics only.
This device contains protection circuitry to protect the inputs against damage due to high static voltages or electric fields; how-
ever, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this
high-impedance circuit. A destructive high current mode may occur if Vin and Vout are not constrained to the range VSS
≤
(Vin or
Vout)
≤
VDD.
Due to the sourcing capability of this circuit, damage can occur to the device if VDD is applied, and the outputs are shorted to
VSS and are at a logical 1 (See Maximum Ratings).
Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD).
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