參數(shù)資料
型號： MC14LC5540DW
廠商： Freescale Semiconductor
文件頁數(shù)： 22/28頁
文件大?。?/td> 0K
描述： IC CODEC ADPCM 28-SOIC W
標準包裝： 26
類型： ADPCM 編解碼器/濾波器
數(shù)據(jù)接口： PCM 音頻接口
分辨率（位）： 13 b
ADC / DAC 數(shù)量： 1 / 1
三角積分調(diào)變： 無
電壓 - 電源，數(shù)字： 4.5V ~ 5.5V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC W
包裝： 管件
MC145484
MOTOROLA
3
PIN DESCRIPTIONS
POWER SUPPLY
VDD
Positive Power Supply (Pin 6)
This is the most positive power supply and is typically con-
nected to + 5 V. This pin should be decoupled to VSS with a
0.1
F ceramic capacitor.
VSS
Negative Power Supply (Pin 15)
This is the most negative power supply and is typically
connected to 0 V.
VAG
Analog Ground Output (Pin 20)
This output pin provides a mid–supply analog ground. This
pin should be decoupled to VSS with a 0.01 F ceramic
capacitor. All analog signal processing within this device is
referenced to this pin. If the audio signals to be processed
are referenced to VSS, then special precautions must be
utilized to avoid noise between VSS and the VAG pin. Refer to
the applications information in this document for more in-
formation. The VAG pin becomes high impedance when this
device is in the powered–down mode.
VAG Ref
Analog Ground Reference Bypass (Pin 1)
This pin is used to capacitively bypass the on–chip cir-
cuitry that generates the mid–supply voltage for the VAG out-
put pin. This pin should be bypassed to VSS with a 0.1 F
ceramic capacitor using short, low inductance traces. The
VAG Ref pin is only used for generating the reference voltage
for the VAG pin. Nothing is to be connected to this pin in addi-
tion to the bypass capacitor. All analog signal processing
within this device is referenced to the VAG pin. If the audio
signals to be processed are referenced to VSS, then special
precautions must be utilized to avoid noise between VSS and
the VAG pin. Refer to the applications information in this
document for more information. When this device is in the
powered–down mode, the VAG Ref pin is pulled to the VDD
power supply with a non–linear, high–impedance circuit.
CONTROL
Mu/A
Mu/A Law Select (Pin 16)
This pin controls the compression for the encoder and the
expansion for the decoder. Mu–Law companding is selected
when this pin is connected to VDD and A–Law companding is
selected when this pin is connected to VSS.
PDI
Power–Down Input (Pin 10)
This pin puts the device into a low power dissipation mode
when a logic 0 is applied. When this device is powered down,
all of the clocks are gated off and all bias currents are turned
off, which causes RO–, PO–, PO+, TG, VAG, and DT to
become high impedance and the VAG Ref pin is pulled to the
VDD power supply with a non–linear, high–impedance circuit.
The device will operate normally when a logic 1 is applied to
this pin. The device goes through a power–up sequence
when this pin is taken to a logic 1 state, which prevents the
DT PCM output from going low impedance for at least two
FST cycles. The VAG and VAG Ref circuits and the signal pro-
cessing filters must settle out before the DT PCM output or
the RO– receive analog output will represent a valid analog
signal.
ANALOG INTERFACE
TI +
Transmit Analog Input (Non–Inverting) (Pin 19)
This is the non–inverting input of the transmit input gain
setting operational amplifier. This pin accommodates a differ-
ential to single–ended circuit for the input gain setting op
amp. This allows input signals that are referenced to the VSS
pin to be level shifted to the VAG pin with minimum noise.
This pin may be connected to the VAG pin for an inverting
amplifier configuration if the input signal is already refer-
enced to the VAG pin. The common mode range of the TI+
and TI– pins is from 1.2 V, to VDD minus 1.2 V. This is an FET
gate input.
The TI+ pin also serves as a digital input control for the
transmit input multiplexer. Connecting the TI+ pin to VDD will
place this amplifier’s output (TG) into a high–impedance
state, and selects the TG pin to serve as a high–impedance
input to the transmit filter. Connecting the TI+ pin to VSS will
also place this amplifier’s output (TG) into a high–impedance
state, and selects the TI– pin to serve as a high–impedance
input to the transmit filter.
TI–
Transmit Analog Input (Inverting) (Pin 18)
This is the inverting input of the transmit gain setting op-
erational amplifier. Gain setting resistors are usually con-
nected from this pin to TG and from this pin to the analog
signal source. The common mode range of the TI+ and TI–
pins is from 1.2 V to VDD – 1.2 V. This is an FET gate input.
The TI– pin also serves as one of the transmit input multi-
plexer pins when the TI+ pin is connected to VSS. When TI+
is connected to VDD, this pin is ignored. See the pin descrip-
tions for the TI+ and the TG pins for more information.
TG
Transmit Gain (Pin 17)
This is the output of the transmit gain setting operational
amplifier and the input to the transmit band–pass filter. This
op amp is capable of driving a 2 k
load. Connecting the TI+
pin to VDD will place the TG pin into a high–impedance state,
and selects the TG pin to serve as a high–impedance input to
the transmit filter. All signals at this pin are referenced to the
VAG pin. When TI+ is connected to VSS, this pin is ignored.
See the pin descriptions for the TI+ and TI– pins for more in-
formation. This pin is high impedance when the device is in
the powered–down mode.
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Freescale Semiconductor, Inc.
For More Information On This Product,
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