參數(shù)資料
型號(hào)： MC14581BCL
廠商： ON SEMICONDUCTOR
元件分類： 算術(shù)邏輯單元
英文描述： 4-BIT ARITHMETIC LOGIC UNIT, CDIP24
封裝： CERAMIC, DIP-24
文件頁數(shù)： 3/7頁
文件大?。?/td> 230K
代理商： MC14581BCL
MOTOROLA CMOS LOGIC DATA
3
MC14581B
SWITCHING CHARACTERISTICS* (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
VDD
Min
Typ #
Max
Unit
Output Rise and Fall Time
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 9.5 ns
tTLH,
tTHL
5.0
10
15
—
100
50
40
200
100
80
ns
Propagation Delay Time
Sum in to Sum Out
tPLH, tPHL = (1.7 ns/pF) CL + 620 ns
tPLH, tPHL = (0.66 ns/pF) CL + 217 ns
tPLH, tPHL = (0.5 ns/pF) CL + 155 ns
tPLH,
tPHL
5.0
10
15
—
705
250
180
1410
500
360
ns
Sum in to Sum Out (Logic Mode)
tPLH, tPHL = (1.7 ns/pF) CL + 520 ns
tPLH, tPHL = (0.66 ns/pF) CL + 182 ns
tPLH, tPHL = (0.5 ns/pF) CL + 155 ns
tPLH,
tPHL
5.0
10
15
—
605
215
180
1210
430
360
ns
Sum in to A = B
tPLH, tPHL = (1.7 ns/pF) CL + 870 ns
tPLH, tPHL = (0.66 ns/pF) CL + 297 ns
tPLH, tPHL = (0.5 ns/pF) CL + 220 ns
tPLH,
tPHL
5.0
10
15
—
955
330
245
1910
660
490
ns
Sum in to P or G
tPLH, tPHL = (1.7 ns/pF) CL + 400 ns
tPLH, tPHL = (0.66 ns/pF) CL + 147 ns
tPLH, tPHL = (0.5 ns/pF) CL + 105 ns
tPLH,
tPHL
5.0
10
15
—
485
180
130
970
360
260
ns
Sum in to Cn+4
tPLH, tPHL = (1.7 ns/pF) CL + 530 ns
tPLH, tPHL = (0.66 ns/pF) CL + 187 ns
tPLH, tPHL = (0.5 ns/pF) CL + 135 ns
tPLH
5.0
10
15
—
615
220
160
1230
440
360
ns
Carry in to Sum Out
tPLH, tPHL = (1.7 ns/pF) CL + 295 ns
tPLH, tPHL = (0.66 ns/pF) CL + 112 ns
tPLH, tPHL = (0.5 ns/pF) CL + 80 ns
tPLH,
tPHL
5.0
10
15
—
380
145
105
760
290
210
ns
Carry in to Cn+4
tPLH, tPHL = (1.7 ns/pF) CL + 220 ns
tPLH, tPHL = (0.66 ns/pF) CL + 87 ns
tPLH, tPHL = (0.5 ns/pF) CL + 60 ns
tPLH,
tPHL
5.0
10
15
—
305
120
85
610
240
170
ns
* The formulas given are for the typical characteristics only at 25
_C.
#Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
AC TEST SETUP REFERENCE TABLE
Test
AC Paths
DC Data Inputs
Mode
Fig. 3
Waveform
Test
Inputs
Outputs
To VSS
To VDD
Mode
Fig. 3
Waveform
Sumin to Sumout
Delay Time
A0
Any F
Remaining A’s
Cn
All B’s
Add
#1
Sumin to P
Delay Time
A0
P
Remaining A’s
Cn
All B’s
Add
#1
Sumin to G
Delay Time
B0
G
All A’s
Cn
Remaining B’s
Add
#1
Sumin to Cn+4
Delay Time
B0
Cn+y
All A’s
Cn
Remaining B’s
Add
#2
Cn to Sumout
Delay Time
Cn
Any F
All A’s
All B’s
Add
#1
Cn to Cn+4
Delay Time
Cn
Cn+4
All A’s
All B’s
Add
#1
Sumin to A = B
Delay Time
A0
A = B
All B’s
Remaining A’s
Cn
Sub
#2
Sumin to Sumout
Delay Time
(Logic Mode)
B0
Any F
All A’s
M
Exclusive
OR
#2
相關(guān)PDF資料
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