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參數(shù)資料
| 型號： | MC14569BDW |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 9/13頁 |
| 文件大小： | 0K |
| 描述： | IC COUNTER DUAL 4BIT 1:4 16-SOIC |
| 產(chǎn)品變化通告： | LTB Notification 03/Jan/2008 |
| 標(biāo)準(zhǔn)包裝： | 47 |
| 系列： | 4000B |
| 邏輯類型： | 除以 N |
| 元件數(shù)： | 2 |
| 每個元件的位元數(shù)： | 4 |
| 復(fù)位： | 異步 |
| 計數(shù)速率： | 13MHz |
| 觸發(fā)器類型： | 正邊沿 |
| 電源電壓： | 3 V ~ 18 V |
| 工作溫度： | -55°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 管件 |
MC14569B
http://onsemi.com
5
PIN DESCRIPTIONS
INPUTS
P0, P1, P2, P3 (Pins 3, 4, 5, 6) Preset Inputs.
Programmable inputs for the least significant counter. May
be binary or BCD depending on the control input.
P4, P5, P6, P7 (Pins 11, 12, 13, 14) Preset Inputs.
Programmable inputs for the most significant counter. May
be binary or BCD depending on the control input.
Clock (Pin 9) Preset data is decremented by one on each
positive transition of this signal.
OUTPUTS
Zero Detect (Pin 1) This output is normally low and
goes high for one clock cycle when the counter has
decremented to zero.
Q (Pin 15) Output of the last stage of the most significant
counter. This output will be inactive unless the preset input
P7 has been set high.
CONTROLS
Cascade Feedback (Pin 7) This pin is normally set
high. When low, loading of the preset inputs (P0 through P7)
is inhibited, i.e., P0 through P7 are “don’t cares.” Refer to
Table 1 for output characteristics.
CTL1 (Pin 2) This pin controls the counting mode of the
least significant counter. When set high, counting mode is
BCD. When set low, counting mode is binary.
CTL2 (Pin 10) This pin controls the counting mode of
the most significant counter. When set high, counting mode
is BCD. When set low, counting mode is binary.
SUPPLY PINS
VSS (Pin 18) Negative Supply Voltage. This pin is
usually connected to ground.
VDD (Pin 16) Positive Supply Voltage. This pin is
connected to a positive supply voltage ranging from 3.0 V
to 18 V.
OPERATING CHARACTERISTICS
The MC14569B is a programmable dividebyN dual
4bit down counter. This counter may be programmed (i.e.,
preset) in BCD or binary code through inputs P0 to P7. For
each counter, the counting sequence may be chosen
independently by applying a high (for BCD count) or a low
(for binary count) to the control inputs CTL1 and CTL2.
The divide ratio N (N being the value programmed on the
preset inputs P0 to P7) is automatically loaded into the
counter as soon as the count 1 is detected. Therefore, a
division ratio of one is not possible. After N clock cycles,
one pulse appears on the Zero Detect output. (See Timing
Diagram.) The Q output is the output of the last stage of the
most significant counter (See Tables 1 through 5, Mode
Controls.)
When cascading the MC14569B to the MC14526B, the
Cascade Feedback input, Q, and Zero Detect outputs must
be respectively connected to “0”, Clock, and Load of the
following counter. If the MC14569B is used alone, Cascade
Feedback must be connected to VDD.
18
16
14
12
10
8.0
6.0
4.0
2.0
0
+ 100
+80
+60
+40
+20
0
-20
-40
TA, AMBIENT TEMPERATURE (°C)
f,FREQUENCY
(MHz),
TYPICAL
CL = 50 pF
VDD = 15 V
10 V
5.0 V
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