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參數(shù)資料
| 型號(hào)： | MC14569BCP |
| 廠商： | MOTOROLA INC |
| 元件分類： | 通用總線功能 |
| 英文描述： | Programmable Divide-By-N Dual 4-Bit Binary/BCD Down Counter |
| 中文描述： | 4000/14000/40000 SERIES, ASYN POSITIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDIP16 |
| 封裝： | PLASTIC, DIP-16 |
| 文件頁(yè)數(shù)： | 4/12頁(yè) |
| 文件大小： | 323K |
| 代理商： | MC14569BCP |
MOTOROLA CMOS LOGIC DATA
MC14569B
4
PIN DESCRIPTIONS
INPUTS
P0, P1, P2, P3 (Pins 3, 4, 5, 6)
— Preset Inputs. Program-
mable inputs for the least significant counter. May be binary
or BCD depending on the control input.
P4, P5, P6, P7 (Pins 11, 12, 13, 14)
—
Preset Inputs. Pro-
grammable inputs for the most significant counter. May be
binary or BCD depending on the control input.
Clock (Pin 9)
— Preset data is decremented by one on
each positive transition of this signal.
OUTPUTS
Zero Detect (Pin 1)
— This output is normally low and
goes high for one clock cycle when the counter has decrem-
ented to zero.
Q (Pin 15)
— Output of the last stage of the most signifi-
cant counter. This output will be inactive unless the preset
input P7 has been set high.
CONTROLS
Cascade Feedback (Pin 7)
— This pin is normally set
high. When low, loading of the preset inputs (P0 through P7)
is inhibited, i.e., P0 through P7 are “don’t cares.” Refer to
Table 1 for output characteristics.
CTL1 (Pin 2)
— This pin controls the counting mode of the
least significant counter. When set high, counting mode is
BCD. When set low, counting mode is binary.
CTL2 (Pin 10)
— This pin controls the counting mode of
the most significant counter. When set high, counting mode
is BCD. When set low, counting mode is binary.
SUPPLY PINS
VSS (Pin 18)
— Negative Supply Voltage. This pin is usual-
ly connected to ground.
VDD (Pin 16)
— Positive Supply Voltage. This pin is con-
nected to a positive supply voltage ranging from 3.0 volts to
18.0 volts.
OPERATING CHARACTERISTICS
The MC14569B is a programmable divide–by–N dual 4–bit
down counter. This counter may be programmed (i.e., pre-
set) in BCD or binary code through inputs P0 to P7. For each
counter, the counting sequence may be chosen indepen-
dently by applying a high (for BCD count) or a low (for binary
count) to the control inputs CTL1 and CTL2.
The divide ratio N (N being the value programmed on the
preset inputs P0 to P7) is automatically loaded into the
counter as soon as the count 1 is detected. Therefore, a divi-
sion ratio of one is not possible. After N clock cycles, one
pulse appears on the Zero Detect output. (See Timing Dia-
gram.) The Q output is the output of the last stage of the most
significant counter (See Tables 1 through 5, Mode Controls.)
When cascading the MC14569B to the MC14568B,
MC14522B or the MC14526B, the Cascade Feedback input,
Q, and Zero Detect outputs must be respectively connected
to “0”, Clock, and Load of the following counter. If the
MC14569B is used alone, Cascade Feedback must be con-
nected to VDD.
13
14
15
16
9
10
11
12
5
4
3
2
1
8
7
6
P5
P6
P7
Q
VDD
CLOCK
CTL2
P4
P1
P0
CTL1
ZERO
DETECT
VSS
CASCADE
FEEDBACK
P3
P2
PIN ASSIGNMENT
18
16
14
12
10
8.0
6.0
4.0
2.0
0
+100
+80
+60
+40
+20
0
–20
–40
TA, AMBIENT TEMPERATURE (
°
C)
f
CL = 50 pF
VDD = 15 V
10 V
5.0 V
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| MC14569BCPG | 功能描述:計(jì)數(shù)器移位寄存器 3-18V Divide-By-N Dual 4-Bit Binary RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
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| MC14569BDWG | 功能描述:計(jì)數(shù)器移位寄存器 3-18V Divide-By-N Dual 4-Bit Binary RoHS:否 制造商:Texas Instruments 計(jì)數(shù)器類型: 計(jì)數(shù)順序:Serial to Serial/Parallel 電路數(shù)量:1 封裝 / 箱體:SOIC-20 Wide 邏輯系列: 邏輯類型: 輸入線路數(shù)量:1 輸出類型:Open Drain 傳播延遲時(shí)間:650 ns 最大工作溫度:+ 125 C 最小工作溫度:- 40 C 封裝:Reel |
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