參數(shù)資料
型號: MC14561BCP
廠商: MOTOROLA INC
元件分類: 通用總線功能
英文描述: Dual-Processor Supervisory Circuits with Power-Fail 8-MSOP -40 to 85
中文描述: 4000/14000/40000 SERIES, 4-BIT ENCODER, PDIP14
封裝: PLASTIC, DIP-14
文件頁數(shù): 1/8頁
文件大小: 178K
代理商: MC14561BCP
MOTOROLA CMOS LOGIC DATA
Motorola, Inc. 1995
1
MC14561B
The MC14561B 9’s complementer is a companion to the MC14560B
NBCD adder to allow BCD subtraction. A BCD number (8–4–2–1 code) is
applied to the inputs (A1 = 20, A2 = 21, A3 = 22, A4 = 23). If the complement
control (Comp) is low, the BCD number appears at the outputs unmodified.
The complement disable (Comp) allows the complement control to be gated,
or an inverted control signal to be used. If the complement input is high and
the disable input low, the 9’s complement of the number is displayed at the
outputs. The zero control (Z), when high, forces the outputs low regardless of
the state of the other inputs.
When the MC14561B is used to perform BCD subtraction in conjunction
with the MC14560B NBCD adder, the complement control becomes an
add/subtract control.
All Inputs Buffered
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–Power TTL Loads or One Low–Power
MAXIMUM RATINGS*
(Voltages Referenced to VSS)
Symbol
Parameter
VDD
DC Supply Voltage
Vin, Vout
Input or Output Voltage (DC or Transient)
Iin, Iout
Input or Output Current (DC or Transient),
per Pin
Value
Unit
– 0.5 to + 18.0
V
– 0.5 to VDD + 0.5
±
10
V
mA
PD
Tstg
TL
Power Dissipation, per Package
500
mW
Storage Temperature
– 65 to + 150
C
Lead Temperature (8–Second Soldering)
260
C
* Maximum Ratings are those values beyond which damage to the device may occur.
Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
TRUTH TABLE
Z
Comp
Comp
F1
F2
F3
F4
Mode
0
0
0
0
0
1
A1
A2
A3
A4
Straight–through
0
1
1
0
1
0
A1
A2
A2A3 + A2A3
A2A3A4
Complement
1
X
X
0
0
0
0
Zero
X = Don’t Care.
SEMICONDUCTOR TECHNICAL DATA
REV 3
1/94
This device contains protection circuitry to
guard against damage due to high static
voltages or electric fields. However, pre-
cautions must be taken to avoid applications of
any voltage higher than maximum rated volt-
ages to this high–impedance circuit. For proper
operation, Vin and Vout should be constrained
to the range VSS
(Vin or Vout)
Unused inputs must always be tied to an
appropriate logic voltage level (e.g., either VSS
or VDD). Unused outputs must be left open.
VDD.
L SUFFIX
CERAMIC
CASE 632
ORDERING INFORMATION
MC14XXXBCP
MC14XXXBCL
MC14XXXBD
TA = – 55
°
to 125
°
C for all packages.
Plastic
Ceramic
SOIC
P SUFFIX
PLASTIC
CASE 646
D SUFFIX
SOIC
CASE 751A
PIN ASSIGNMENT
11
12
13
14
8
9
10
5
4
3
2
1
7
6
F4
F3
F2
F1
VDD
NC
Z
A4
A3
A2
A1
VSS
COMP
COMP
NC = NO CONNECTION
相關PDF資料
PDF描述
MC14561BD 9’s Complementer
MC14562BCL 128-Bit Static Shift Register
MC14562 128-Bit Static Shift Register
MC14562B 128-Bit Static Shift Register
MC14562BCP 128-Bit Static Shift Register
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