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參數(shù)資料
| 型號(hào)： | MC14559BCL |
| 廠商： | MOTOROLA INC |
| 元件分類： | 標(biāo)準(zhǔn)邏輯 |
| 英文描述： | Successive Approximation Registers |
| 中文描述： | SPECIALTY LOGIC CIRCUIT, CDIP16 |
| 封裝： | CERAMIC, DIP-16 |
| 文件頁數(shù)： | 6/9頁 |
| 文件大?。?/td> | 209K |
| 代理商： | MC14559BCL |
MOTOROLA CMOS LOGIC DATA
MC14549B MC14559B
6
TYPICAL APPLICATIONS
Externally Controlled 6–Bit ADC (Figure 2)
Several features are shown in this application:
Shortening of the register to six bits by feeding the seventh
output bit into the FF input.
Continuous conversion, if a continuous signal is applied to
SC.
Externally controlled updating (the start pulse must be
shorter than the conversion cycle).
The EOC output indicating that the parallel data are valid
and that the serial output is complete.
Continuously Cycling 8–Bit ADC (Figure 3)
This ADC is running continuously because the EOC signal
is fed back to the SC input, immediately initiating a new cycle
on the next clock pulse.
Continuously Cycling 12–Bit ADC (Figure 4)
Because each successive approximation register (SAR)
has a capability of handling only an eight–bit word, two must
be cascaded to make an ADC with more than eight bits.
When it is necessary to cascade two SAR’s, the second
SAR must have a stable resettable state to remain in while
awaiting a subsequent start signal. However, the first stage
must not have a stable resettable state while recycling, be-
cause during switch–on or due to outside influences, the first
stage has entered a reset state, the entire ADC will remain in
a stable non–functional condition.
This 12–bit ADC is continuously recycling. The serial as
well as the parallel outputs are updated every thirteenth
clock pulse. The EOC pulse indicates the completion of
Figure 2. Externally Controlled 6–Bit ADC
TO DAC
SC
C
Sout
Q7 Q6
Q5
MC14559B
Q4
Q3
Q2
Q1
Q0
EOC
FF
Figure 3. Continuously Cycling 8–Bit ADC
TO DAC
SC
C
Sout
Q7 Q6
Q5
MC14559B
Q4
Q3
Q2
Q1
Q0
EOC
FF
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| MC14559BCP | 功能描述:寄存器 LOG CMOS SHIFT REG APPROX RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| MC14559BCPG | 功能描述:寄存器 LOG CMOS SHIFT REG APPROX RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| MC14559BDWR2 | 功能描述:寄存器 LOG CMOS SHIFT REG APPROX RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| MC14559BDWR2G | 功能描述:寄存器 LOG CMOS SHIFT REG APPROX RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| MC1455BD | 功能描述:計(jì)時(shí)器和支持產(chǎn)品 ANA TIMING CIRCUIT RoHS:否 制造商:Micrel 類型:Standard 封裝 / 箱體:SOT-23 內(nèi)部定時(shí)器數(shù)量:1 電源電壓-最大:18 V 電源電壓-最小:2.7 V 最大功率耗散: 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝:Reel |
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